Commit 7335631f authored by Linus Walleij's avatar Linus Walleij Committed by Stephen Boyd
Browse files

dt-bindings: clock: u8500: Add clkout clock bindings 



This adds device tree bindings for the externally routed clocks
CLKOUT1 and CLKOUT2 clocks found in the DB8500.

Cc: devicetree@vger.kernel.org
Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220414221751.323525-2-linus.walleij@linaro.org


Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 31231092

Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml

+57 −0
Original line number Diff line number Diff line
@@ -109,6 +109,25 @@ properties: 


    additionalProperties: false



  clkout-clock:

    description: A subnode with three clock cells for externally routed clocks,

      output clocks. These are two PRCMU-internal clocks that can be divided and

      muxed out on the pads of the DB8500 SoC.

    type: object



    properties:

      '#clock-cells':

        description:

          The first cell indicates which output clock we are using,

          possible values are 0 (CLKOUT1) and 1 (CLKOUT2).

          The second cell indicates which clock we want to use as source,

          possible values are 0 thru 7, see the defines for the different

          source clocks.

          The third cell is a divider, legal values are 1 thru 63.

        const: 3



    additionalProperties: false



required:

  - compatible

  - reg
@@ -119,3 +138,41 @@ required: 
  - smp-twd-clock



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/ste-db8500-clkout.h>

    clocks@8012 {

      compatible = "stericsson,u8500-clks";

      reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,

            <0x8000f000 0x1000>, <0xa03ff000 0x1000>,

            <0xa03cf000 0x1000>;



      prcmu_clk: prcmu-clock {

        #clock-cells = <1>;

      };



      prcc_pclk: prcc-periph-clock {

        #clock-cells = <2>;

      };



      prcc_kclk: prcc-kernel-clock {

        #clock-cells = <2>;

      };



      prcc_reset: prcc-reset-controller {

        #reset-cells = <2>;

      };



      rtc_clk: rtc32k-clock {

        #clock-cells = <0>;

      };



      smp_twd_clk: smp-twd-clock {

        #clock-cells = <0>;

      };



      clkout_clk: clkout-clock {

        #clock-cells = <3>;

      };

    };

include/dt-bindings/clock/ste-db8500-clkout.h

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+17 −0
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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __STE_CLK_DB8500_CLKOUT_H__

#define __STE_CLK_DB8500_CLKOUT_H__



#define DB8500_CLKOUT_1			0

#define DB8500_CLKOUT_2			1



#define DB8500_CLKOUT_SRC_CLK38M	0

#define DB8500_CLKOUT_SRC_ACLK		1

#define DB8500_CLKOUT_SRC_SYSCLK	2

#define DB8500_CLKOUT_SRC_LCDCLK	3

#define DB8500_CLKOUT_SRC_SDMMCCLK	4

#define DB8500_CLKOUT_SRC_TVCLK		5

#define DB8500_CLKOUT_SRC_TIMCLK	6

#define DB8500_CLKOUT_SRC_CLK009	7



#endif