Commit 732d69c8 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/misc-6.1 into irq/irqchip-next



* irq/misc-6.1:
  : .
  : Misc irqchip updates for 6.1:
  :
  : - Allow generic irqchip support without selecting CONFIG_OF_IRQ
  :
  : - Fix a couple of bindings for TI interrupts controllers
  :
  : - Yet another binding update for a Renesas SoC
  :
  : - The obligatory fixes from the spelling police
  : .
  dt-bindings: irqchip: renesas,irqc: Add r8a779g0 support
  irqchip/gic-v3: Fix typo in comment
  dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding
  dt-bindings: irqchip: ti,sci-inta: Fix warning for missing #interrupt-cells
  irqchip: Make irqchip_init() usable on pure ACPI systems

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents aa280808 872f3a4e
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+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ properties:
          - renesas,intc-ex-r8a77990    # R-Car E3
          - renesas,intc-ex-r8a77995    # R-Car D3
          - renesas,intc-ex-r8a779a0    # R-Car V3U
          - renesas,intc-ex-r8a779g0    # R-Car V4H
      - const: renesas,irqc

  '#interrupt-cells':
+3 −0
Original line number Diff line number Diff line
@@ -59,6 +59,9 @@ properties:

  interrupt-controller: true

  '#interrupt-cells':
    const: 0

  msi-controller: true

  ti,interrupt-ranges:
+3 −0
Original line number Diff line number Diff line
@@ -58,6 +58,9 @@ properties:
        1 = If intr supports edge triggered interrupts.
        4 = If intr supports level triggered interrupts.

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ menu "IRQ chip support"

config IRQCHIP
	def_bool y
	depends on OF_IRQ
	depends on (OF_IRQ || ACPI_GENERIC_GSI)

config ARM_GIC
	bool
+1 −1
Original line number Diff line number Diff line
@@ -978,7 +978,7 @@ static int __gic_update_rdist_properties(struct redist_region *region,
	u64 typer = gic_read_typer(ptr + GICR_TYPER);
	u32 ctlr = readl_relaxed(ptr + GICR_CTLR);

	/* Boot-time cleanip */
	/* Boot-time cleanup */
	if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
		u64 val;

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