Commit 72fb3b60 authored by Moshe Shemesh's avatar Moshe Shemesh Committed by Saeed Mahameed
Browse files

net/mlx5: Add reset_state field to MFRL register 



Add new field reset_state to MFRL register. This field expose current
state of sync reset for fw update. This field enables sharing with the
user more details on why fw activate failed in case it failed the sync
reset stage.

Signed-off-by: default avatarMoshe Shemesh <moshe@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent c76a1e90

include/linux/mlx5/mlx5_ifc.h

+12 −2
Original line number Diff line number Diff line
@@ -9694,7 +9694,8 @@ struct mlx5_ifc_pcam_reg_bits { 
};



struct mlx5_ifc_mcam_enhanced_features_bits {

	u8         reserved_at_0[0x6b];

	u8         reserved_at_0[0x6a];

	u8         reset_state[0x1];

	u8         ptpcyc2realtime_modify[0x1];

	u8         reserved_at_6c[0x2];

	u8         pci_status_and_power[0x1];
@@ -10375,6 +10376,14 @@ struct mlx5_ifc_mcda_reg_bits { 
	u8         data[][0x20];

};



enum {

	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,

	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,

	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,

	MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,

	MLX5_MFRL_REG_RESET_STATE_NACK = 4,

};



enum {

	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),

	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
@@ -10393,7 +10402,8 @@ struct mlx5_ifc_mfrl_reg_bits { 
	u8         pci_sync_for_fw_update_start[0x1];

	u8         pci_sync_for_fw_update_resp[0x2];

	u8         rst_type_sel[0x3];

	u8         reserved_at_28[0x8];

	u8         reserved_at_28[0x4];

	u8         reset_state[0x4];

	u8         reset_type[0x8];

	u8         reset_level[0x8];

};