Commit 72d6b245 authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Thierry Reding
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pwm: iqs620a: Fix overflow and optimize calculations



If state->duty_cycle is 0x100000000000000, the previous calculation of
duty_scale overflows and yields a duty cycle ratio of 0% instead of
100%. Fix this by clamping the requested duty cycle to the maximal
possible duty cycle first. This way it is possible to use a native
integer division instead of a (depending on the architecture) more
expensive 64bit division.

With this change in place duty_scale cannot be bigger than 256 which
allows to simplify the calculation of duty_val.

Fixes: 6f0841a8 ("pwm: Add support for Azoteq IQS620A PWM generator")
Tested-by: default avatarJeff LaBundy <jeff@labundy.com>
Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 11be938a
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+5 −3
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
	struct iqs620_pwm_private *iqs620_pwm;
	struct iqs62x_core *iqs62x;
	u64 duty_scale;
	unsigned int duty_cycle;
	unsigned int duty_scale;
	int ret;

	if (state->polarity != PWM_POLARITY_NORMAL)
@@ -70,7 +71,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
	 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to
	 * allow an external pull-down resistor to hold the GPIO3/LTX pin low.
	 */
	duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);
	duty_cycle = min_t(u64, state->duty_cycle, IQS620_PWM_PERIOD_NS);
	duty_scale = duty_cycle * 256 / IQS620_PWM_PERIOD_NS;

	mutex_lock(&iqs620_pwm->lock);

@@ -82,7 +84,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
	}

	if (duty_scale) {
		u8 duty_val = min_t(u64, duty_scale - 1, 0xff);
		u8 duty_val = duty_scale - 1;

		ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
				   duty_val);