Commit 72a949c1 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Junhao He
Browse files

coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE 

mainline inclusion
from mainline-v6.4-rc1
commit ab5ca626
category: Feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I89N5L
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ab5ca6268afcc470e7c9b2d66b0eb9f178755260

----------------------------------------------------------------------

Instead of adding the PIDs forever to the list for the new CPUs, let us detect
a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and
DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID
matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RAO) always.

Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com


Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: frowand.list@gmail.com
Cc: linux@armlinux.org.uk
Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
[ Fixed typo in the description RA0 => RAO ]
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230605133031.1827626-1-suzuki.poulose@arm.com


Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
parent 12c8cfe2

drivers/hwtracing/coresight/coresight-etm4x-core.c

+5 −0
Original line number Diff line number Diff line
@@ -2130,6 +2130,11 @@ static const struct amba_id etm4_ids[] = { 
	CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */

	CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */

	CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */

	/*

	 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new

	 * CPUs to the list here.

	 */

	CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),

	{},

};

drivers/hwtracing/coresight/coresight-priv.h

+17 −2
Original line number Diff line number Diff line
@@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void); 
	}



/* coresight AMBA ID, full UCI structure: id table entry. */

#define CS_AMBA_UCI_ID(pid, uci_ptr)		\

#define __CS_AMBA_UCI_ID(pid, m, uci_ptr)	\

	{					\

		.id	= pid,			\

		.mask	= 0x000fffff,		\

		.mask	= m,			\

		.data	= (void *)uci_ptr	\

	}

#define CS_AMBA_UCI_ID(pid, uci)	__CS_AMBA_UCI_ID(pid, 0x000fffff, uci)

/*

 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the

 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that

 * as a match value for blanket matching all devices in the given CoreSight

 * device type and architecture.

 */

#define PIDR2_JEDEC			BIT(3)

#define PID_PIDR2_JEDEC			(PIDR2_JEDEC << 16)

/*

 * Match all PIDs in a given CoreSight device type and architecture, defined

 * by the uci.

 */

#define CS_AMBA_MATCH_ALL_UCI(uci)					\

	__CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)



/* extract the data value from a UCI structure given amba_id pointer. */

static inline void *coresight_get_uci_data(const struct amba_id *id)