Unverified Commit 72a21285 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.19-dt-bindings' of... 

Merge tag 'tegra-for-5.19-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.19-rc1

Updates the memory controller bindings to properly validate the number
of entries in the reg and reg-names properties.

* tag 'tegra-for-5.19-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: memory: tegra: Update validation for reg and reg-names

Link: https://lore.kernel.org/r/20220506143005.3916655-3-thierry.reding@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 50a54337 e2ab93e5

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml

+74 −6
Original line number Diff line number Diff line
@@ -34,8 +34,12 @@ properties: 
          - nvidia,tegra234-mc



  reg:

    minItems: 1

    maxItems: 3

    minItems: 6

    maxItems: 18



  reg-names:

    minItems: 6

    maxItems: 18



  interrupts:

    items:
@@ -142,7 +146,18 @@ allOf: 
    then:

      properties:

        reg:

          maxItems: 1

          maxItems: 6

          description: 5 memory controller channels and 1 for stream-id registers



        reg-names:

          maxItems: 6

          items:

            - const: sid

            - const: broadcast

            - const: ch0

            - const: ch1

            - const: ch2

            - const: ch3



  - if:

      properties:
@@ -151,7 +166,30 @@ allOf: 
    then:

      properties:

        reg:

          minItems: 3

          minItems: 18

          description: 17 memory controller channels and 1 for stream-id registers



        reg-names:

          minItems: 18

          items:

            - const: sid

            - const: broadcast

            - const: ch0

            - const: ch1

            - const: ch2

            - const: ch3

            - const: ch4

            - const: ch5

            - const: ch6

            - const: ch7

            - const: ch8

            - const: ch9

            - const: ch10

            - const: ch11

            - const: ch12

            - const: ch13

            - const: ch14

            - const: ch15



  - if:

      properties:
@@ -160,13 +198,37 @@ allOf: 
    then:

      properties:

        reg:

          minItems: 3

          minItems: 18

          description: 17 memory controller channels and 1 for stream-id registers



        reg-names:

          minItems: 18

          items:

            - const: sid

            - const: broadcast

            - const: ch0

            - const: ch1

            - const: ch2

            - const: ch3

            - const: ch4

            - const: ch5

            - const: ch6

            - const: ch7

            - const: ch8

            - const: ch9

            - const: ch10

            - const: ch11

            - const: ch12

            - const: ch13

            - const: ch14

            - const: ch15



additionalProperties: false



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - "#address-cells"

  - "#size-cells"
@@ -182,7 +244,13 @@ examples: 


        memory-controller@2c00000 {

            compatible = "nvidia,tegra186-mc";

            reg = <0x0 0x02c00000 0x0 0xb0000>;

            reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */

                  <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */

                  <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */

                  <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */

                  <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */

                  <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */

            reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";

            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;



            #address-cells = <2>;