Loading arch/mips/include/asm/uasm.h +1 −0 Original line number Diff line number Diff line Loading @@ -141,6 +141,7 @@ Ip_u2u1u3(_sra); Ip_u2u1u3(_srl); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); Ip_u1(_sync); Ip_u1(_syscall); Ip_0(_tlbp); Ip_0(_tlbr); Loading arch/mips/mm/uasm-micromips.c +1 −0 Original line number Diff line number Diff line Loading @@ -99,6 +99,7 @@ static struct insn insn_table_MM[] = { { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS }, { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, Loading arch/mips/mm/uasm-mips.c +1 −0 Original line number Diff line number Diff line Loading @@ -107,6 +107,7 @@ static struct insn insn_table[] = { { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE }, { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, Loading arch/mips/mm/uasm.c +3 −2 Original line number Diff line number Diff line Loading @@ -53,8 +53,8 @@ enum opcode { insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, }; struct insn { Loading Loading @@ -271,6 +271,7 @@ I_u2u1u3(_srl) I_u2u1u3(_rotr) I_u3u1u2(_subu) I_u2s3u1(_sw) I_u1(_sync) I_0(_tlbp) I_0(_tlbr) I_0(_tlbwi) Loading Loading
arch/mips/include/asm/uasm.h +1 −0 Original line number Diff line number Diff line Loading @@ -141,6 +141,7 @@ Ip_u2u1u3(_sra); Ip_u2u1u3(_srl); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); Ip_u1(_sync); Ip_u1(_syscall); Ip_0(_tlbp); Ip_0(_tlbr); Loading
arch/mips/mm/uasm-micromips.c +1 −0 Original line number Diff line number Diff line Loading @@ -99,6 +99,7 @@ static struct insn insn_table_MM[] = { { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS }, { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, Loading
arch/mips/mm/uasm-mips.c +1 −0 Original line number Diff line number Diff line Loading @@ -107,6 +107,7 @@ static struct insn insn_table[] = { { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE }, { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, Loading
arch/mips/mm/uasm.c +3 −2 Original line number Diff line number Diff line Loading @@ -53,8 +53,8 @@ enum opcode { insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, }; struct insn { Loading Loading @@ -271,6 +271,7 @@ I_u2u1u3(_srl) I_u2u1u3(_rotr) I_u3u1u2(_subu) I_u2s3u1(_sw) I_u1(_sync) I_0(_tlbp) I_0(_tlbr) I_0(_tlbwi) Loading