Commit 723e3671 authored by Rex-BC Chen's avatar Rex-BC Chen Committed by Stephen Boyd
Browse files

clk: mediatek: reset: Support nonsequence base offsets of reset registers 



The bank offsets are not serial for all reset registers.
For example, there are five infra reset banks for MT8192: 0x120, 0x130,
0x140, 0x150 and 0x730.

To support this,
- Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
  the reset register.
- Add a new define RST_NR_PER_BANK to define reset number for each
  reset bank.

Signed-off-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 2d2a2900

drivers/clk/mediatek/clk-mt2701-eth.c

+4 −2
Original line number Diff line number Diff line
@@ -36,10 +36,12 @@ static const struct mtk_gate eth_clks[] = { 
	GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),

};



static u16 rst_ofs[] = { 0x34, };



static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SIMPLE,

	.rst_bank_nr = 1,

	.reg_ofs = 0x34,

	.rst_bank_ofs = rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(rst_ofs),

};



static const struct of_device_id of_match_clk_mt2701_eth[] = {

drivers/clk/mediatek/clk-mt2701-g3d.c

+4 −2
Original line number Diff line number Diff line
@@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] = { 
	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),

};



static u16 rst_ofs[] = { 0xc, };



static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SIMPLE,

	.rst_bank_nr = 1,

	.reg_ofs = 0xc,

	.rst_bank_ofs = rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(rst_ofs),

};



static int clk_mt2701_g3dsys_init(struct platform_device *pdev)

drivers/clk/mediatek/clk-mt2701-hif.c

+4 −2
Original line number Diff line number Diff line
@@ -33,10 +33,12 @@ static const struct mtk_gate hif_clks[] = { 
	GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),

};



static u16 rst_ofs[] = { 0x34, };



static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SIMPLE,

	.rst_bank_nr = 1,

	.reg_ofs = 0x34,

	.rst_bank_ofs = rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(rst_ofs),

};



static const struct of_device_id of_match_clk_mt2701_hif[] = {

drivers/clk/mediatek/clk-mt2701.c

+7 −4
Original line number Diff line number Diff line
@@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { 
	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),

};



static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };

static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };



static const struct mtk_clk_rst_desc clk_rst_desc[] = {

	/* infrasys */

	{

		.version = MTK_RST_SIMPLE,

		.rst_bank_nr = 2,

		.reg_ofs = 0x30,

		.rst_bank_ofs = infrasys_rst_ofs,

		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),

	},

	/* pericfg */

	{

		.version = MTK_RST_SIMPLE,

		.rst_bank_nr = 2,

		.reg_ofs = 0x0,

		.rst_bank_ofs = pericfg_rst_ofs,

		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),

	},

};

drivers/clk/mediatek/clk-mt2712.c

+7 −4
Original line number Diff line number Diff line
@@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = { 
		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),

};



static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };

static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };



static const struct mtk_clk_rst_desc clk_rst_desc[] = {

	/* infra */

	{

		.version = MTK_RST_SIMPLE,

		.rst_bank_nr = 2,

		.reg_ofs = 0x30,

		.rst_bank_ofs = infrasys_rst_ofs,

		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),

	},

	/* peri */

	{

		.version = MTK_RST_SIMPLE,

		.rst_bank_nr = 2,

		.reg_ofs = 0x0,

		.rst_bank_ofs = pericfg_rst_ofs,

		.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),

	},

};