Commit 7232c132 authored by Tal Gilboa's avatar Tal Gilboa Committed by Jason Gunthorpe
Browse files

RDMA/mlx5: Allow CQ creation without attached EQs 

The traditional DevX CQ creation flow goes through mlx5_core_create_cq()
which checks that the given EQN corresponds to an existing EQ and attaches
a devx handler to the EQN for the CQ.

In some cases the EQ will not be a kernel EQ, but will be controlled by
modify CQ, don't block creating these just because the EQN can't be found
in the kernel.

Link: https://lore.kernel.org/r/20210211085549.1277674-1-leon@kernel.org


Signed-off-by: default avatarTal Gilboa <talgi@nvidia.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@nvidia.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent e2853c49

drivers/infiniband/hw/mlx5/devx.c

+12 −1
Original line number Diff line number Diff line
@@ -1439,6 +1439,16 @@ static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) 
	rcu_read_unlock();

}



static bool is_apu_thread_cq(struct mlx5_ib_dev *dev, const void *in)

{

	if (!MLX5_CAP_GEN(dev->mdev, apu) ||

	    !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context),

		      apu_thread_cq))

		return false;



	return true;

}



static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)(

	struct uverbs_attr_bundle *attrs)

{
@@ -1492,7 +1502,8 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)( 
		obj->flags |= DEVX_OBJ_FLAGS_DCT;

		err = mlx5_core_create_dct(dev, &obj->core_dct, cmd_in,

					   cmd_in_len, cmd_out, cmd_out_len);

	} else if (opcode == MLX5_CMD_OP_CREATE_CQ) {

	} else if (opcode == MLX5_CMD_OP_CREATE_CQ &&

		   !is_apu_thread_cq(dev, cmd_in)) {

		obj->flags |= DEVX_OBJ_FLAGS_CQ;

		obj->core_cq.comp = devx_cq_comp;

		err = mlx5_core_create_cq(dev->mdev, &obj->core_cq,

include/linux/mlx5/mlx5_ifc.h

+3 −2
Original line number Diff line number Diff line
@@ -1634,7 +1634,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { 
	u8         sf_set_partition[0x1];

	u8         reserved_at_682[0x1];

	u8         log_max_sf[0x5];

	u8         reserved_at_688[0x8];

	u8         apu[0x1];

	u8         reserved_at_689[0x7];

	u8         log_min_sf_size[0x8];

	u8         max_num_sf_partitions[0x8];
@@ -3816,7 +3817,7 @@ struct mlx5_ifc_cqc_bits { 
	u8         status[0x4];

	u8         reserved_at_4[0x2];

	u8         dbr_umem_valid[0x1];

	u8         reserved_at_7[0x1];

	u8         apu_thread_cq[0x1];

	u8         cqe_sz[0x3];

	u8         cc[0x1];

	u8         reserved_at_c[0x1];