Commit 722dc8a1 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Stephen Boyd
Browse files

dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC 



New compatible to manage clock and reset of STM32MP13 SoC.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20220516070600.7692-2-gabriel.fernandez@foss.st.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 31231092

Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ description: | 


  The list of valid indices for STM32MP1 is available in:

  include/dt-bindings/reset-controller/stm32mp1-resets.h

  include/dt-bindings/reset-controller/stm32mp13-resets.h



  This file implements defines like:

  #define LTDC_R	3072
@@ -57,6 +58,7 @@ properties: 
      - enum:

          - st,stm32mp1-rcc-secure

          - st,stm32mp1-rcc

          - st,stm32mp13-rcc

      - const: syscon



  reg:

include/dt-bindings/clock/stm32mp13-clks.h

0 → 100644
+229 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */

/*

 * Copyright (C) STMicroelectronics 2020 - All Rights Reserved

 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

 */



#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_

#define _DT_BINDINGS_STM32MP13_CLKS_H_



/* OSCILLATOR clocks */

#define CK_HSE		0

#define CK_CSI		1

#define CK_LSI		2

#define CK_LSE		3

#define CK_HSI		4

#define CK_HSE_DIV2	5



/* PLL */

#define PLL1		6

#define PLL2		7

#define PLL3		8

#define PLL4		9



/* ODF */

#define PLL1_P		10

#define PLL1_Q		11

#define PLL1_R		12

#define PLL2_P		13

#define PLL2_Q		14

#define PLL2_R		15

#define PLL3_P		16

#define PLL3_Q		17

#define PLL3_R		18

#define PLL4_P		19

#define PLL4_Q		20

#define PLL4_R		21



#define PCLK1		22

#define PCLK2		23

#define PCLK3		24

#define PCLK4		25

#define PCLK5		26

#define PCLK6		27



/* SYSTEM CLOCK */

#define CK_PER		28

#define CK_MPU		29

#define CK_AXI		30

#define CK_MLAHB	31



/* BASE TIMER */

#define CK_TIMG1	32

#define CK_TIMG2	33

#define CK_TIMG3	34



/* AUX */

#define RTC		35



/* TRACE & DEBUG clocks */

#define CK_DBG		36

#define CK_TRACE	37



/* MCO clocks */

#define CK_MCO1		38

#define CK_MCO2		39



/*  IP clocks */

#define SYSCFG		40

#define VREF		41

#define DTS		42

#define PMBCTRL		43

#define HDP		44

#define IWDG2		45

#define STGENRO		46

#define USART1		47

#define RTCAPB		48

#define TZC		49

#define TZPC		50

#define IWDG1		51

#define BSEC		52

#define DMA1		53

#define DMA2		54

#define DMAMUX1		55

#define DMAMUX2		56

#define GPIOA		57

#define GPIOB		58

#define GPIOC		59

#define GPIOD		60

#define GPIOE		61

#define GPIOF		62

#define GPIOG		63

#define GPIOH		64

#define GPIOI		65

#define CRYP1		66

#define HASH1		67

#define BKPSRAM		68

#define MDMA		69

#define CRC1		70

#define USBH		71

#define DMA3		72

#define TSC		73

#define PKA		74

#define AXIMC		75

#define MCE		76

#define ETH1TX		77

#define ETH2TX		78

#define ETH1RX		79

#define ETH2RX		80

#define ETH1MAC		81

#define ETH2MAC		82

#define ETH1STP		83

#define ETH2STP		84



/* IP clocks with parents */

#define SDMMC1_K	85

#define SDMMC2_K	86

#define ADC1_K		87

#define ADC2_K		88

#define FMC_K		89

#define QSPI_K		90

#define RNG1_K		91

#define USBPHY_K	92

#define STGEN_K		93

#define SPDIF_K		94

#define SPI1_K		95

#define SPI2_K		96

#define SPI3_K		97

#define SPI4_K		98

#define SPI5_K		99

#define I2C1_K		100

#define I2C2_K		101

#define I2C3_K		102

#define I2C4_K		103

#define I2C5_K		104

#define TIM2_K		105

#define TIM3_K		106

#define TIM4_K		107

#define TIM5_K		108

#define TIM6_K		109

#define TIM7_K		110

#define TIM12_K		111

#define TIM13_K		112

#define TIM14_K		113

#define TIM1_K		114

#define TIM8_K		115

#define TIM15_K		116

#define TIM16_K		117

#define TIM17_K		118

#define LPTIM1_K	119

#define LPTIM2_K	120

#define LPTIM3_K	121

#define LPTIM4_K	122

#define LPTIM5_K	123

#define USART1_K	124

#define USART2_K	125

#define USART3_K	126

#define UART4_K		127

#define UART5_K		128

#define USART6_K	129

#define UART7_K		130

#define UART8_K		131

#define DFSDM_K		132

#define FDCAN_K		133

#define SAI1_K		134

#define SAI2_K		135

#define ADFSDM_K	136

#define USBO_K		137

#define LTDC_PX		138

#define ETH1CK_K	139

#define ETH1PTP_K	140

#define ETH2CK_K	141

#define ETH2PTP_K	142

#define DCMIPP_K	143

#define SAES_K		144

#define DTS_K		145



/* DDR */

#define DDRC1		146

#define DDRC1LP		147

#define DDRC2		148

#define DDRC2LP		149

#define DDRPHYC		150

#define DDRPHYCLP	151

#define DDRCAPB		152

#define DDRCAPBLP	153

#define AXIDCG		154

#define DDRPHYCAPB	155

#define DDRPHYCAPBLP	156

#define DDRPERFM	157



#define ADC1		158

#define ADC2		159

#define SAI1		160

#define SAI2		161



#define STM32MP1_LAST_CLK 162



/* SCMI clock identifiers */

#define CK_SCMI_HSE		0

#define CK_SCMI_HSI		1

#define CK_SCMI_CSI		2

#define CK_SCMI_LSE		3

#define CK_SCMI_LSI		4

#define CK_SCMI_HSE_DIV2	5

#define CK_SCMI_PLL2_Q		6

#define CK_SCMI_PLL2_R		7

#define CK_SCMI_PLL3_P		8

#define CK_SCMI_PLL3_Q		9

#define CK_SCMI_PLL3_R		10

#define CK_SCMI_PLL4_P		11

#define CK_SCMI_PLL4_Q		12

#define CK_SCMI_PLL4_R		13

#define CK_SCMI_MPU		14

#define CK_SCMI_AXI		15

#define CK_SCMI_MLAHB		16

#define CK_SCMI_CKPER		17

#define CK_SCMI_PCLK1		18

#define CK_SCMI_PCLK2		19

#define CK_SCMI_PCLK3		20

#define CK_SCMI_PCLK4		21

#define CK_SCMI_PCLK5		22

#define CK_SCMI_PCLK6		23

#define CK_SCMI_CKTIMG1		24

#define CK_SCMI_CKTIMG2		25

#define CK_SCMI_CKTIMG3		26

#define CK_SCMI_RTC		27

#define CK_SCMI_RTCAPB		28



#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */

include/dt-bindings/reset/stm32mp13-resets.h

0 → 100644
+100 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */

/*

 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved

 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

 */



#ifndef _DT_BINDINGS_STM32MP13_RESET_H_

#define _DT_BINDINGS_STM32MP13_RESET_H_



#define TIM2_R		13568

#define TIM3_R		13569

#define TIM4_R		13570

#define TIM5_R		13571

#define TIM6_R		13572

#define TIM7_R		13573

#define LPTIM1_R	13577

#define SPI2_R		13579

#define SPI3_R		13580

#define USART3_R	13583

#define UART4_R		13584

#define UART5_R		13585

#define UART7_R		13586

#define UART8_R		13587

#define I2C1_R		13589

#define I2C2_R		13590

#define SPDIF_R		13594

#define TIM1_R		13632

#define TIM8_R		13633

#define SPI1_R		13640

#define USART6_R	13645

#define SAI1_R		13648

#define SAI2_R		13649

#define DFSDM_R		13652

#define FDCAN_R		13656

#define LPTIM2_R	13696

#define LPTIM3_R	13697

#define LPTIM4_R	13698

#define LPTIM5_R	13699

#define SYSCFG_R	13707

#define VREF_R		13709

#define DTS_R		13712

#define PMBCTRL_R	13713

#define LTDC_R		13760

#define DCMIPP_R	13761

#define DDRPERFM_R	13768

#define USBPHY_R	13776

#define STGEN_R		13844

#define USART1_R	13888

#define USART2_R	13889

#define SPI4_R		13890

#define SPI5_R		13891

#define I2C3_R		13892

#define I2C4_R		13893

#define I2C5_R		13894

#define TIM12_R		13895

#define TIM13_R		13896

#define TIM14_R		13897

#define TIM15_R		13898

#define TIM16_R		13899

#define TIM17_R		13900

#define DMA1_R		13952

#define DMA2_R		13953

#define DMAMUX1_R	13954

#define DMA3_R		13955

#define DMAMUX2_R	13956

#define ADC1_R		13957

#define ADC2_R		13958

#define USBO_R		13960

#define GPIOA_R		14080

#define GPIOB_R		14081

#define GPIOC_R		14082

#define GPIOD_R		14083

#define GPIOE_R		14084

#define GPIOF_R		14085

#define GPIOG_R		14086

#define GPIOH_R		14087

#define GPIOI_R		14088

#define TSC_R		14095

#define PKA_R		14146

#define SAES_R		14147

#define CRYP1_R		14148

#define HASH1_R		14149

#define RNG1_R		14150

#define AXIMC_R		14160

#define MDMA_R		14208

#define MCE_R		14209

#define ETH1MAC_R	14218

#define FMC_R		14220

#define QSPI_R		14222

#define SDMMC1_R	14224

#define SDMMC2_R	14225

#define CRC1_R		14228

#define USBH_R		14232

#define ETH2MAC_R	14238



/* SCMI reset domain identifiers */

#define RST_SCMI_LTDC		0

#define RST_SCMI_MDMA		1



#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */