Commit 71f69ffa authored by Ashish Singhal's avatar Ashish Singhal Committed by Thierry Reding
Browse files

arm64: tegra: Add QSPI controllers on Tegra234 



This adds the QSPI controllers on the Tegra234 SoC and populates the
SPI NOR flash device for the Jetson AGX Orin platform.

Signed-off-by: default avatarAshish Singhal <ashishsingha@nvidia.com>
Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarKrishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: default avatarJon Hunter <jonathanh@nvidia.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 7ac853ba

arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -7,6 +7,18 @@ 
	compatible = "nvidia,p3701-0000", "nvidia,tegra234";



	bus@0 {

		spi@3270000 {

			status = "okay";



			flash@0 {

				compatible = "jedec,spi-nor";

				reg = <0>;

				spi-max-frequency = <102000000>;

				spi-tx-bus-width = <4>;

				spi-rx-bus-width = <4>;

			};

		};



		mmc@3460000 {

			status = "okay";

			bus-width = <8>;

arch/arm64/boot/dts/nvidia/tegra234.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -654,6 +654,20 @@ 
			reset-names = "i2c";

		};



		spi@3270000 {

			compatible = "nvidia,tegra234-qspi";

			reg = <0x3270000 0x1000>;

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,

				 <&bpmp TEGRA234_CLK_QSPI0_PM>;

			clock-names = "qspi", "qspi_out";

			resets = <&bpmp TEGRA234_RESET_QSPI0>;

			reset-names = "qspi";

			status = "disabled";

		};



		pwm1: pwm@3280000 {

			compatible = "nvidia,tegra194-pwm",

				     "nvidia,tegra186-pwm";
@@ -666,6 +680,20 @@ 
			#pwm-cells = <2>;

		};



		spi@3300000 {

			compatible = "nvidia,tegra234-qspi";

			reg = <0x3300000 0x1000>;

			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,

				 <&bpmp TEGRA234_CLK_QSPI1_PM>;

			clock-names = "qspi", "qspi_out";

			resets = <&bpmp TEGRA234_RESET_QSPI1>;

			reset-names = "qspi";

			status = "disabled";

		};



		mmc@3460000 {

			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";

			reg = <0x03460000 0x20000>;

include/dt-bindings/clock/tegra234-clock.h

+8 −0
Original line number Diff line number Diff line
@@ -140,6 +140,14 @@ 
#define TEGRA234_CLK_PEX2_C9_CORE		173U

/** @brief output of gate CLK_ENB_PEX2_CORE_10 */

#define TEGRA234_CLK_PEX2_C10_CORE		187U

/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */

#define TEGRA234_CLK_QSPI0_2X_PM		192U

/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */

#define TEGRA234_CLK_QSPI1_2X_PM		193U

/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */

#define TEGRA234_CLK_QSPI0_PM			194U

/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */

#define TEGRA234_CLK_QSPI1_PM			195U

/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */

#define TEGRA234_CLK_SDMMC_LEGACY_TM		219U

/** @brief output of gate CLK_ENB_PEX0_CORE_0 */

include/dt-bindings/reset/tegra234-reset.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
#define TEGRA234_RESET_PWM6			73U

#define TEGRA234_RESET_PWM7			74U

#define TEGRA234_RESET_PWM8			75U

#define TEGRA234_RESET_QSPI0			76U

#define TEGRA234_RESET_QSPI1			77U

#define TEGRA234_RESET_SDMMC4			85U

#define TEGRA234_RESET_UARTA			100U

#define TEGRA234_RESET_PEX0_CORE_0		116U