Commit 71de5b23 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qca8081-phy-driver' 



Luo Jie says:

====================
net: phy: Add qca8081 ethernet phy driver

This patch series add the qca8081 ethernet phy driver support, which
improve the wol feature, leverage at803x phy driver and add the fast
retrain, master/slave seed and CDT feature.

Changes in v7:
	* update Reviewed-by tags.

Changes in v6:
	* add Reviewed-by tags on the applicable patches.

Changes in v5:
	* rebase the patches on net-next/master.

Changes in v4:
	* handle other interrupts in set_wol.
	* add genphy_c45_fast_retrain.

Changes in v3:
	* correct a typo "excpet".
	* remove the suffix "PHY" from phy name.

Changes in v2:
	* add definitions of fast retrain related registers in mdio.h.
	* break up the patch into small patches.
	* improve the at803x legacy code.

Changes in v1:
	* merge qca8081 phy driver into at803x.
	* add cdt feature.
	* leverage at803x phy driver helpers.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 0b87074b 8c84d752

drivers/net/phy/at803x.c

+533 −47
Original line number Diff line number Diff line
@@ -33,14 +33,17 @@ 
#define AT803X_SFC_DISABLE_JABBER		BIT(0)



#define AT803X_SPECIFIC_STATUS			0x11

#define AT803X_SS_SPEED_MASK			(3 << 14)

#define AT803X_SS_SPEED_1000			(2 << 14)

#define AT803X_SS_SPEED_100			(1 << 14)

#define AT803X_SS_SPEED_10			(0 << 14)

#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)

#define AT803X_SS_SPEED_1000			2

#define AT803X_SS_SPEED_100			1

#define AT803X_SS_SPEED_10			0

#define AT803X_SS_DUPLEX			BIT(13)

#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)

#define AT803X_SS_MDIX				BIT(6)



#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)

#define QCA808X_SS_SPEED_2500			4



#define AT803X_INTR_ENABLE			0x12

#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)

#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
@@ -70,7 +73,8 @@ 
#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)

#define AT803X_LED_CONTROL			0x18



#define AT803X_DEVICE_ADDR			0x03

#define AT803X_PHY_MMD3_WOL_CTRL		0x8012

#define AT803X_WOL_EN				BIT(5)

#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C

#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B

#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
@@ -157,6 +161,8 @@ 
#define ATH8035_PHY_ID				0x004dd072

#define AT8030_PHY_ID_MASK			0xffffffef



#define QCA8081_PHY_ID				0x004dd101



#define QCA8327_A_PHY_ID			0x004dd033

#define QCA8327_B_PHY_ID			0x004dd034

#define QCA8337_PHY_ID				0x004dd036
@@ -172,7 +178,84 @@ 
#define AT803X_KEEP_PLL_ENABLED			BIT(0)

#define AT803X_DISABLE_SMARTEEE			BIT(1)



MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");

/* ADC threshold */

#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80

#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)

#define QCA808X_ADC_THRESHOLD_80MV		0

#define QCA808X_ADC_THRESHOLD_100MV		0xf0

#define QCA808X_ADC_THRESHOLD_200MV		0x0f

#define QCA808X_ADC_THRESHOLD_300MV		0xff



/* CLD control */

#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007

#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)

#define QCA808X_8023AZ_AFE_EN			0x90



/* AZ control */

#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008

#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32



#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014

#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529



#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E

#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341



#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E

#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419



#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020

#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341



#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c

#define QCA808X_TOP_OPTION1_DATA		0x0



#define QCA808X_PHY_MMD3_DEBUG_1		0xa100

#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203

#define QCA808X_PHY_MMD3_DEBUG_2		0xa101

#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad

#define QCA808X_PHY_MMD3_DEBUG_3		0xa103

#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698

#define QCA808X_PHY_MMD3_DEBUG_4		0xa105

#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001

#define QCA808X_PHY_MMD3_DEBUG_5		0xa106

#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111

#define QCA808X_PHY_MMD3_DEBUG_6		0xa011

#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85



/* master/slave seed config */

#define QCA808X_PHY_DEBUG_LOCAL_SEED		9

#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)

#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)

#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32



/* Hibernation yields lower power consumpiton in contrast with normal operation mode.

 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.

 */

#define QCA808X_DBG_AN_TEST			0xb

#define QCA808X_HIBERNATION_EN			BIT(15)



#define QCA808X_CDT_ENABLE_TEST			BIT(15)

#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)

#define QCA808X_CDT_LENGTH_UNIT			BIT(10)



#define QCA808X_MMD3_CDT_STATUS			0x8064

#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065

#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066

#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067

#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068

#define QCA808X_CDT_DIAG_LENGTH			GENMASK(7, 0)



#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)

#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)

#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)

#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)

#define QCA808X_CDT_STATUS_STAT_FAIL		0

#define QCA808X_CDT_STATUS_STAT_NORMAL		1

#define QCA808X_CDT_STATUS_STAT_OPEN		2

#define QCA808X_CDT_STATUS_STAT_SHORT		3



MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");

MODULE_AUTHOR("Matus Ujhelyi");

MODULE_LICENSE("GPL");
@@ -336,9 +419,9 @@ static int at803x_set_wol(struct phy_device *phydev, 
{

	struct net_device *ndev = phydev->attached_dev;

	const u8 *mac;

	int ret;

	u32 value;

	unsigned int i, offsets[] = {

	int ret, irq_enabled;

	unsigned int i;

	const unsigned int offsets[] = {

		AT803X_LOC_MAC_ADDR_32_47_OFFSET,

		AT803X_LOC_MAC_ADDR_16_31_OFFSET,

		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
@@ -354,25 +437,48 @@ static int at803x_set_wol(struct phy_device *phydev, 
			return -EINVAL;



		for (i = 0; i < 3; i++)

			phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],

			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],

				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));



		value = phy_read(phydev, AT803X_INTR_ENABLE);

		value |= AT803X_INTR_ENABLE_WOL;

		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);

		/* Enable WOL function */

		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,

				0, AT803X_WOL_EN);

		if (ret)

			return ret;

		/* Enable WOL interrupt */

		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);

		if (ret)

			return ret;

		value = phy_read(phydev, AT803X_INTR_STATUS);

	} else {

		value = phy_read(phydev, AT803X_INTR_ENABLE);

		value &= (~AT803X_INTR_ENABLE_WOL);

		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);

		/* Disable WoL function */

		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,

				AT803X_WOL_EN, 0);

		if (ret)

			return ret;

		/* Disable WOL interrupt */

		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);

		if (ret)

			return ret;

		value = phy_read(phydev, AT803X_INTR_STATUS);

	}



	/* Clear WOL status */

	ret = phy_read(phydev, AT803X_INTR_STATUS);

	if (ret < 0)

		return ret;



	/* Check if there are other interrupts except for WOL triggered when PHY is

	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can

	 * be passed up to the interrupt PIN.

	 */

	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);

	if (irq_enabled < 0)

		return irq_enabled;



	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;

	if (ret & irq_enabled && !phy_polling_mode(phydev))

		phy_trigger_machine(phydev);



	return 0;

}



static void at803x_get_wol(struct phy_device *phydev,
@@ -383,8 +489,11 @@ static void at803x_get_wol(struct phy_device *phydev, 
	wol->supported = WAKE_MAGIC;

	wol->wolopts = 0;



	value = phy_read(phydev, AT803X_INTR_ENABLE);

	if (value & AT803X_INTR_ENABLE_WOL)

	value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL);

	if (value < 0)

		return;



	if (value & AT803X_WOL_EN)

		wol->wolopts |= WAKE_MAGIC;

}
@@ -712,6 +821,15 @@ static int at803x_get_features(struct phy_device *phydev) 
	if (err)

		return err;



	if (phydev->drv->phy_id == QCA8081_PHY_ID) {

		err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);

		if (err < 0)

			return err;



		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,

				err & MDIO_PMA_NG_EXTABLE_2_5GBT);

	}



	if (phydev->drv->phy_id != ATH8031_PHY_ID)

		return 0;
@@ -930,27 +1048,9 @@ static void at803x_link_change_notify(struct phy_device *phydev) 
	}

}



static int at803x_read_status(struct phy_device *phydev)

static int at803x_read_specific_status(struct phy_device *phydev)

{

	int ss, err, old_link = phydev->link;



	/* Update the link, but return if there was an error */

	err = genphy_update_link(phydev);

	if (err)

		return err;



	/* why bother the PHY if nothing can have changed */

	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)

		return 0;



	phydev->speed = SPEED_UNKNOWN;

	phydev->duplex = DUPLEX_UNKNOWN;

	phydev->pause = 0;

	phydev->asym_pause = 0;



	err = genphy_read_lpa(phydev);

	if (err < 0)

		return err;

	int ss;



	/* Read the AT8035 PHY-Specific Status register, which indicates the

	 * speed and duplex that the PHY is actually using, irrespective of
@@ -961,13 +1061,19 @@ static int at803x_read_status(struct phy_device *phydev) 
		return ss;



	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {

		int sfc;

		int sfc, speed;



		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);

		if (sfc < 0)

			return sfc;



		switch (ss & AT803X_SS_SPEED_MASK) {

		/* qca8081 takes the different bits for speed value from at803x */

		if (phydev->drv->phy_id == QCA8081_PHY_ID)

			speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);

		else

			speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);



		switch (speed) {

		case AT803X_SS_SPEED_10:

			phydev->speed = SPEED_10;

			break;
@@ -977,6 +1083,9 @@ static int at803x_read_status(struct phy_device *phydev) 
		case AT803X_SS_SPEED_1000:

			phydev->speed = SPEED_1000;

			break;

		case QCA808X_SS_SPEED_2500:

			phydev->speed = SPEED_2500;

			break;

		}

		if (ss & AT803X_SS_DUPLEX)

			phydev->duplex = DUPLEX_FULL;
@@ -1001,6 +1110,35 @@ static int at803x_read_status(struct phy_device *phydev) 
		}

	}



	return 0;

}



static int at803x_read_status(struct phy_device *phydev)

{

	int err, old_link = phydev->link;



	/* Update the link, but return if there was an error */

	err = genphy_update_link(phydev);

	if (err)

		return err;



	/* why bother the PHY if nothing can have changed */

	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)

		return 0;



	phydev->speed = SPEED_UNKNOWN;

	phydev->duplex = DUPLEX_UNKNOWN;

	phydev->pause = 0;

	phydev->asym_pause = 0;



	err = genphy_read_lpa(phydev);

	if (err < 0)

		return err;



	err = at803x_read_specific_status(phydev);

	if (err < 0)

		return err;



	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)

		phy_resolve_aneg_pause(phydev);
@@ -1048,7 +1186,30 @@ static int at803x_config_aneg(struct phy_device *phydev) 
			return ret;

	}



	return genphy_config_aneg(phydev);

	/* Do not restart auto-negotiation by setting ret to 0 defautly,

	 * when calling __genphy_config_aneg later.

	 */

	ret = 0;



	if (phydev->drv->phy_id == QCA8081_PHY_ID) {

		int phy_ctrl = 0;



		/* The reg MII_BMCR also needs to be configured for force mode, the

		 * genphy_config_aneg is also needed.

		 */

		if (phydev->autoneg == AUTONEG_DISABLE)

			genphy_c45_pma_setup_forced(phydev);



		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))

			phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;



		ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,

				MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);

		if (ret < 0)

			return ret;

	}



	return __genphy_config_aneg(phydev, ret);

}



static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
@@ -1184,6 +1345,12 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) 
{

	u16 cdt;



	/* qca8081 takes the different bit 15 to enable CDT test */

	if (phydev->drv->phy_id == QCA8081_PHY_ID)

		cdt = QCA808X_CDT_ENABLE_TEST |

			QCA808X_CDT_LENGTH_UNIT |

			QCA808X_CDT_INTER_CHECK_DIS;

	else

		cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |

			AT803X_CDT_ENABLE_TEST;
@@ -1193,10 +1360,16 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) 
static int at803x_cdt_wait_for_completion(struct phy_device *phydev)

{

	int val, ret;

	u16 cdt_en;



	if (phydev->drv->phy_id == QCA8081_PHY_ID)

		cdt_en = QCA808X_CDT_ENABLE_TEST;

	else

		cdt_en = AT803X_CDT_ENABLE_TEST;



	/* One test run takes about 25ms */

	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,

				    !(val & AT803X_CDT_ENABLE_TEST),

				    !(val & cdt_en),

				    30000, 100000, true);



	return ret < 0 ? ret : 0;
@@ -1405,6 +1578,298 @@ static int qca83xx_suspend(struct phy_device *phydev) 
	return 0;

}



static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)

{

	int ret;



	/* Enable fast retrain */

	ret = genphy_c45_fast_retrain(phydev, true);

	if (ret)

		return ret;



	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,

			QCA808X_TOP_OPTION1_DATA);

	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,

			QCA808X_MSE_THRESHOLD_20DB_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,

			QCA808X_MSE_THRESHOLD_17DB_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,

			QCA808X_MSE_THRESHOLD_27DB_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,

			QCA808X_MSE_THRESHOLD_28DB_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,

			QCA808X_MMD3_DEBUG_1_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,

			QCA808X_MMD3_DEBUG_4_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,

			QCA808X_MMD3_DEBUG_5_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,

			QCA808X_MMD3_DEBUG_3_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,

			QCA808X_MMD3_DEBUG_6_VALUE);

	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,

			QCA808X_MMD3_DEBUG_2_VALUE);



	return 0;

}



static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev)

{

	u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE);



	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,

			QCA808X_MASTER_SLAVE_SEED_CFG,

			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value));

}



static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)

{

	u16 seed_enable = 0;



	if (enable)

		seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE;



	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,

			QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable);

}



static int qca808x_config_init(struct phy_device *phydev)

{

	int ret;



	/* Active adc&vga on 802.3az for the link 1000M and 100M */

	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,

			QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);

	if (ret)

		return ret;



	/* Adjust the threshold on 802.3az for the link 1000M */

	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,

			QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);

	if (ret)

		return ret;



	/* Config the fast retrain for the link 2500M */

	ret = qca808x_phy_fast_retrain_config(phydev);

	if (ret)

		return ret;



	/* Configure lower ramdom seed to make phy linked as slave mode */

	ret = qca808x_phy_ms_random_seed_set(phydev);

	if (ret)

		return ret;



	/* Enable seed */

	ret = qca808x_phy_ms_seed_enable(phydev, true);

	if (ret)

		return ret;



	/* Configure adc threshold as 100mv for the link 10M */

	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,

			QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);

}



static int qca808x_read_status(struct phy_device *phydev)

{

	int ret;



	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);

	if (ret < 0)

		return ret;



	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,

			ret & MDIO_AN_10GBT_STAT_LP2_5G);



	ret = genphy_read_status(phydev);

	if (ret)

		return ret;



	ret = at803x_read_specific_status(phydev);

	if (ret < 0)

		return ret;



	if (phydev->link && phydev->speed == SPEED_2500)

		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;

	else

		phydev->interface = PHY_INTERFACE_MODE_SMII;



	/* generate seed as a lower random value to make PHY linked as SLAVE easily,

	 * except for master/slave configuration fault detected.

	 * the reason for not putting this code into the function link_change_notify is

	 * the corner case where the link partner is also the qca8081 PHY and the seed

	 * value is configured as the same value, the link can't be up and no link change

	 * occurs.

	 */

	if (!phydev->link) {

		if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {

			qca808x_phy_ms_seed_enable(phydev, false);

		} else {

			qca808x_phy_ms_random_seed_set(phydev);

			qca808x_phy_ms_seed_enable(phydev, true);

		}

	}



	return 0;

}



static int qca808x_soft_reset(struct phy_device *phydev)

{

	int ret;



	ret = genphy_soft_reset(phydev);

	if (ret < 0)

		return ret;



	return qca808x_phy_ms_seed_enable(phydev, true);

}



static bool qca808x_cdt_fault_length_valid(int cdt_code)

{

	switch (cdt_code) {

	case QCA808X_CDT_STATUS_STAT_SHORT:

	case QCA808X_CDT_STATUS_STAT_OPEN:

		return true;

	default:

		return false;

	}

}



static int qca808x_cable_test_result_trans(int cdt_code)

{

	switch (cdt_code) {

	case QCA808X_CDT_STATUS_STAT_NORMAL:

		return ETHTOOL_A_CABLE_RESULT_CODE_OK;

	case QCA808X_CDT_STATUS_STAT_SHORT:

		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;

	case QCA808X_CDT_STATUS_STAT_OPEN:

		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;

	case QCA808X_CDT_STATUS_STAT_FAIL:

	default:

		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;

	}

}



static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)

{

	int val;

	u32 cdt_length_reg = 0;



	switch (pair) {

	case ETHTOOL_A_CABLE_PAIR_A:

		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;

		break;

	case ETHTOOL_A_CABLE_PAIR_B:

		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;

		break;

	case ETHTOOL_A_CABLE_PAIR_C:

		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;

		break;

	case ETHTOOL_A_CABLE_PAIR_D:

		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;

		break;

	default:

		return -EINVAL;

	}



	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);

	if (val < 0)

		return val;



	return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;

}



static int qca808x_cable_test_start(struct phy_device *phydev)

{

	int ret;



	/* perform CDT with the following configs:

	 * 1. disable hibernation.

	 * 2. force PHY working in MDI mode.

	 * 3. for PHY working in 1000BaseT.

	 * 4. configure the threshold.

	 */



	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);

	if (ret < 0)

		return ret;



	ret = at803x_config_mdix(phydev, ETH_TP_MDI);

	if (ret < 0)

		return ret;



	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */

	phydev->duplex = DUPLEX_FULL;

	phydev->speed = SPEED_1000;

	ret = genphy_c45_pma_setup_forced(phydev);

	if (ret < 0)

		return ret;



	ret = genphy_setup_forced(phydev);

	if (ret < 0)

		return ret;



	/* configure the thresholds for open, short, pair ok test */

	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);

	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);

	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);

	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);

	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);

	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);



	return 0;

}



static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)

{

	int ret, val;

	int pair_a, pair_b, pair_c, pair_d;



	*finished = false;



	ret = at803x_cdt_start(phydev, 0);

	if (ret)

		return ret;



	ret = at803x_cdt_wait_for_completion(phydev);

	if (ret)

		return ret;



	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);

	if (val < 0)

		return val;



	pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);

	pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);

	pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);

	pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);



	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,

				qca808x_cable_test_result_trans(pair_a));

	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,

				qca808x_cable_test_result_trans(pair_b));

	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,

				qca808x_cable_test_result_trans(pair_c));

	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,

				qca808x_cable_test_result_trans(pair_d));



	if (qca808x_cdt_fault_length_valid(pair_a))

		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,

				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));

	if (qca808x_cdt_fault_length_valid(pair_b))

		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,

				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));

	if (qca808x_cdt_fault_length_valid(pair_c))

		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,

				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));

	if (qca808x_cdt_fault_length_valid(pair_d))

		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,

				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));



	*finished = true;



	return 0;

}



static struct phy_driver at803x_driver[] = {

{

	/* Qualcomm Atheros AR8035 */
@@ -1564,6 +2029,26 @@ static struct phy_driver at803x_driver[] = { 
	.get_stats		= at803x_get_stats,

	.suspend		= qca83xx_suspend,

	.resume			= qca83xx_resume,

}, {

	/* Qualcomm QCA8081 */

	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),

	.name			= "Qualcomm QCA8081",

	.flags			= PHY_POLL_CABLE_TEST,

	.config_intr		= at803x_config_intr,

	.handle_interrupt	= at803x_handle_interrupt,

	.get_tunable		= at803x_get_tunable,

	.set_tunable		= at803x_set_tunable,

	.set_wol		= at803x_set_wol,

	.get_wol		= at803x_get_wol,

	.get_features		= at803x_get_features,

	.config_aneg		= at803x_config_aneg,

	.suspend		= genphy_suspend,

	.resume			= genphy_resume,

	.read_status		= qca808x_read_status,

	.config_init		= qca808x_config_init,

	.soft_reset		= qca808x_soft_reset,

	.cable_test_start	= qca808x_cable_test_start,

	.cable_test_get_status	= qca808x_cable_test_get_status,

}, };



module_phy_driver(at803x_driver);
@@ -1578,6 +2063,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { 
	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },

	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },

	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },

	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },

	{ }

};

drivers/net/phy/phy-c45.c

+34 −0
Original line number Diff line number Diff line
@@ -611,6 +611,40 @@ int genphy_c45_loopback(struct phy_device *phydev, bool enable) 
}

EXPORT_SYMBOL_GPL(genphy_c45_loopback);



/**

 * genphy_c45_fast_retrain - configure fast retrain registers

 * @phydev: target phy_device struct

 *

 * Description: If fast-retrain is enabled, we configure PHY as

 *   advertising fast retrain capable and THP Bypass Request, then

 *   enable fast retrain. If it is not enabled, we configure fast

 *   retrain disabled.

 */

int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)

{

	int ret;



	if (!enable)

		return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,

				MDIO_PMA_10GBR_FSRT_ENABLE);



	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {

		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,

				MDIO_AN_10GBT_CTRL_ADVFSRT2_5G);

		if (ret)

			return ret;



		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,

				MDIO_AN_THP_BP2_5GT);

		if (ret)

			return ret;

	}



	return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,

			MDIO_PMA_10GBR_FSRT_ENABLE);

}

EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);



struct phy_driver genphy_c45_driver = {

	.phy_id         = 0xffffffff,

	.phy_id_mask    = 0xffffffff,

include/linux/phy.h

+1 −0
Original line number Diff line number Diff line
@@ -1584,6 +1584,7 @@ int genphy_c45_config_aneg(struct phy_device *phydev); 
int genphy_c45_loopback(struct phy_device *phydev, bool enable);

int genphy_c45_pma_resume(struct phy_device *phydev);

int genphy_c45_pma_suspend(struct phy_device *phydev);

int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable);



/* Generic C45 PHY driver */

extern struct phy_driver genphy_c45_driver;

include/uapi/linux/mdio.h

+9 −0
Original line number Diff line number Diff line
@@ -53,12 +53,14 @@ 
#define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */

#define MDIO_AN_EEE_ADV2	62	/* EEE advertisement 2 */

#define MDIO_AN_EEE_LPABLE2	63	/* EEE link partner ability 2 */

#define MDIO_AN_CTRL2		64	/* AN THP bypass request control */



/* Media-dependent registers. */

#define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */

#define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */

#define MDIO_PMA_10GBT_SNR	133	/* 10GBASE-T SNR margin, lane A.

					 * Lanes B-D are numbered 134-136. */

#define MDIO_PMA_10GBR_FSRT_CSR	147	/* 10GBASE-R fast retrain status and control */

#define MDIO_PMA_10GBR_FECABLE	170	/* 10GBASE-R FEC ability */

#define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */

#define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
@@ -239,6 +241,9 @@ 
#define MDIO_PMA_10GBR_FECABLE_ABLE	0x0001	/* FEC ability */

#define MDIO_PMA_10GBR_FECABLE_ERRABLE	0x0002	/* FEC error indic. ability */



/* PMA 10GBASE-R Fast Retrain status and control register. */

#define MDIO_PMA_10GBR_FSRT_ENABLE	0x0001	/* Fast retrain enable */



/* PCS 10GBASE-R/-T status register 1. */

#define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */
@@ -247,6 +252,7 @@ 
#define MDIO_PCS_10GBRT_STAT2_BER	0x3f00



/* AN 10GBASE-T control register. */

#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G	0x0020	/* Advertise 2.5GBASE-T fast retrain */

#define MDIO_AN_10GBT_CTRL_ADV2_5G	0x0080	/* Advertise 2.5GBASE-T */

#define MDIO_AN_10GBT_CTRL_ADV5G	0x0100	/* Advertise 5GBASE-T */

#define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */
@@ -289,6 +295,9 @@ 
#define MDIO_EEE_2_5GT		0x0001	/* 2.5GT EEE cap */

#define MDIO_EEE_5GT		0x0002	/* 5GT EEE cap */



/* AN MultiGBASE-T AN control 2 */

#define MDIO_AN_THP_BP2_5GT	0x0008	/* 2.5GT THP bypass request */



/* 2.5G/5G Extended abilities register. */

#define MDIO_PMA_NG_EXTABLE_2_5GBT	0x0001	/* 2.5GBASET ability */

#define MDIO_PMA_NG_EXTABLE_5GBT	0x0002	/* 5GBASET ability */