Commit 71d03935 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-fixes-6.2-1' of... 

Merge tag 'kvmarm-fixes-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master

KVM/arm64 fixes for 6.2, take #1

- Fix the PMCR_EL0 reset value after the PMU rework

- Correctly handle S2 fault triggered by a S1 page table walk
  by not always classifying it as a write, as this breaks on
  R/O memslots

- Document why we cannot exit with KVM_EXIT_MMIO when taking
  a write fault from a S1 PTW on a R/O memslot

- Put the Apple M2 on the naughty step for not being able to
  correctly implement the vgic SEIS feature, just liek the M1
  before it

- Reviewer updates: Alex is stepping down, replaced by Zenghui
parents 3a9ae31a de535c02

Documentation/virt/kvm/api.rst

+8 −0
Original line number Diff line number Diff line
@@ -1354,6 +1354,14 @@ the memory region are automatically reflected into the guest. For example, an 
mmap() that affects the region will be made visible immediately.  Another

example is madvise(MADV_DROP).



Note: On arm64, a write generated by the page-table walker (to update

the Access and Dirty flags, for example) never results in a

KVM_EXIT_MMIO exit when the slot has the KVM_MEM_READONLY flag. This

is because KVM cannot provide the data that would be written by the

page-table walker, making it impossible to emulate the access.

Instead, an abort (data abort if the cause of the page-table update

was a load or a store, instruction abort if it was an instruction

fetch) is injected in the guest.



4.36 KVM_SET_TSS_ADDR

---------------------

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -11356,9 +11356,9 @@ F: virt/kvm/* 
KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)

M:	Marc Zyngier <maz@kernel.org>

R:	James Morse <james.morse@arm.com>

R:	Alexandru Elisei <alexandru.elisei@arm.com>

R:	Suzuki K Poulose <suzuki.poulose@arm.com>

R:	Oliver Upton <oliver.upton@linux.dev>

R:	Zenghui Yu <yuzenghui@huawei.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

L:	kvmarm@lists.linux.dev

L:	kvmarm@lists.cs.columbia.edu (deprecated, moderated for non-subscribers)

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -124,6 +124,8 @@ 
#define APPLE_CPU_PART_M1_FIRESTORM_PRO	0x025

#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028

#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029

#define APPLE_CPU_PART_M2_BLIZZARD	0x032

#define APPLE_CPU_PART_M2_AVALANCHE	0x033



#define AMPERE_CPU_PART_AMPERE1		0xAC3
@@ -177,6 +179,8 @@ 
#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)

#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)

#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)

#define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)

#define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

arch/arm64/include/asm/esr.h

+9 −0
Original line number Diff line number Diff line
@@ -114,6 +114,15 @@ 
#define ESR_ELx_FSC_ACCESS	(0x08)

#define ESR_ELx_FSC_FAULT	(0x04)

#define ESR_ELx_FSC_PERM	(0x0C)

#define ESR_ELx_FSC_SEA_TTW0	(0x14)

#define ESR_ELx_FSC_SEA_TTW1	(0x15)

#define ESR_ELx_FSC_SEA_TTW2	(0x16)

#define ESR_ELx_FSC_SEA_TTW3	(0x17)

#define ESR_ELx_FSC_SECC	(0x18)

#define ESR_ELx_FSC_SECC_TTW0	(0x1c)

#define ESR_ELx_FSC_SECC_TTW1	(0x1d)

#define ESR_ELx_FSC_SECC_TTW2	(0x1e)

#define ESR_ELx_FSC_SECC_TTW3	(0x1f)



/* ISS field definitions for Data Aborts */

#define ESR_ELx_ISV_SHIFT	(24)

arch/arm64/include/asm/kvm_arm.h

+0 −15
Original line number Diff line number Diff line
@@ -319,21 +319,6 @@ 
				 BIT(18) |		\

				 GENMASK(16, 15))



/* For compatibility with fault code shared with 32-bit */

#define FSC_FAULT	ESR_ELx_FSC_FAULT

#define FSC_ACCESS	ESR_ELx_FSC_ACCESS

#define FSC_PERM	ESR_ELx_FSC_PERM

#define FSC_SEA		ESR_ELx_FSC_EXTABT

#define FSC_SEA_TTW0	(0x14)

#define FSC_SEA_TTW1	(0x15)

#define FSC_SEA_TTW2	(0x16)

#define FSC_SEA_TTW3	(0x17)

#define FSC_SECC	(0x18)

#define FSC_SECC_TTW0	(0x1c)

#define FSC_SECC_TTW1	(0x1d)

#define FSC_SECC_TTW2	(0x1e)

#define FSC_SECC_TTW3	(0x1f)



/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */

#define HPFAR_MASK	(~UL(0xf))

/*