Loading arch/ia64/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,7 @@ config IA64 select SYSCTL_ARCH_UNALIGN_NO_WARN select HAVE_MOD_ARCH_SPECIFIC select MODULES_USE_ELF_RELA select ARCH_USE_CMPXCHG_LOCKREF default y help The Itanium Processor Family is Intel's 64-bit successor to Loading arch/ia64/include/asm/spinlock.h +5 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,11 @@ static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1; } static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { return !(((lock.lock >> TICKET_SHIFT) ^ lock.lock) & TICKET_MASK); } static inline int arch_spin_is_locked(arch_spinlock_t *lock) { return __ticket_spin_is_locked(lock); Loading Loading
arch/ia64/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,7 @@ config IA64 select SYSCTL_ARCH_UNALIGN_NO_WARN select HAVE_MOD_ARCH_SPECIFIC select MODULES_USE_ELF_RELA select ARCH_USE_CMPXCHG_LOCKREF default y help The Itanium Processor Family is Intel's 64-bit successor to Loading
arch/ia64/include/asm/spinlock.h +5 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,11 @@ static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1; } static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { return !(((lock.lock >> TICKET_SHIFT) ^ lock.lock) & TICKET_MASK); } static inline int arch_spin_is_locked(arch_spinlock_t *lock) { return __ticket_spin_is_locked(lock); Loading