Commit 719e433e authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdgpu: Fix channel_index table layout for Aldebaran 



Fix the channel_index table layout to fetch the correct
channel_index when calculating physical address from
normalized address during page retirement.
Also, fix the number of UMC instances and number of channels
within each UMC instance for Aldebaran.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-By: default avatarJohn Clements <john.clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8d70136e

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+2 −2
Original line number Diff line number Diff line
@@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 
		break;

	case CHIP_ALDEBARAN:

		adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;

		adev->umc.channel_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;

		adev->umc.umc_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;

		adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;

		adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;

		adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;

		if (!adev->gmc.xgmi.connected_to_cpu)

			adev->umc.ras_funcs = &umc_v6_7_ras_funcs;

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

+8 −8
Original line number Diff line number Diff line
@@ -30,17 +30,17 @@ 


const uint32_t

	umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {

		{28, 12, 6, 22},	{19, 3, 9, 25},

		{20, 4, 30, 14},	{11, 27, 1, 17},

		{24, 8, 2, 18},		{15, 31, 5, 21},

		{16, 0, 26, 10},	{7, 23, 29, 13}

		{28, 20, 24, 16, 12, 4, 8, 0},

		{6, 30, 2, 26, 22, 14, 18, 10},

		{19, 11, 15, 7, 3, 27, 31, 23},

		{9, 1, 5, 29, 25, 17, 21, 13}

};

const uint32_t

	umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {

		{19, 3, 9, 25},		{28, 12, 6, 22},

		{11, 27, 1, 17},	{20, 4, 30, 14},

		{15, 31, 5, 21},	{24, 8, 2, 18},

		{7, 23, 29, 13},	{16, 0, 26, 10}

		{19, 11, 15, 7,	3, 27, 31, 23},

		{9, 1, 5, 29, 25, 17, 21, 13},

		{28, 20, 24, 16, 12, 4, 8, 0},

		{6, 30, 2, 26, 22, 14, 18, 10},

};



static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/umc_v6_7.h

+2 −2
Original line number Diff line number Diff line
@@ -36,9 +36,9 @@ 
#define UMC_V6_7_INST_DIST	0x40000



/* number of umc channel instance with memory map register access */

#define UMC_V6_7_CHANNEL_INSTANCE_NUM		4

#define UMC_V6_7_UMC_INSTANCE_NUM		4

/* number of umc instance with memory map register access */

#define UMC_V6_7_UMC_INSTANCE_NUM		8

#define UMC_V6_7_CHANNEL_INSTANCE_NUM		8

/* total channel instances in one umc block */

#define UMC_V6_7_TOTAL_CHANNEL_NUM	(UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)

/* UMC regiser per channel offset */