Loading arch/tile/include/asm/topology.h +57 −18 Original line number Diff line number Diff line Loading @@ -44,10 +44,44 @@ static inline const struct cpumask *cpumask_of_node(int node) /* For now, use numa node -1 for global allocation. */ #define pcibus_to_node(bus) ((void)(bus), -1) /* * TILE architecture has many cores integrated in one processor, so we need * setup bigger balance_interval for both CPU/NODE scheduling domains to * reduce process scheduling costs. */ /* sched_domains SD_CPU_INIT for TILE architecture */ #define SD_CPU_INIT (struct sched_domain) { \ .min_interval = 4, \ .max_interval = 128, \ .busy_factor = 64, \ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ .busy_idx = 2, \ .idle_idx = 1, \ .newidle_idx = 0, \ .wake_idx = 0, \ .forkexec_idx = 0, \ \ .flags = 1*SD_LOAD_BALANCE \ | 1*SD_BALANCE_NEWIDLE \ | 1*SD_BALANCE_EXEC \ | 1*SD_BALANCE_FORK \ | 0*SD_BALANCE_WAKE \ | 0*SD_WAKE_AFFINE \ | 0*SD_PREFER_LOCAL \ | 0*SD_SHARE_CPUPOWER \ | 0*SD_SHARE_PKG_RESOURCES \ | 0*SD_SERIALIZE \ , \ .last_balance = jiffies, \ .balance_interval = 32, \ } /* sched_domains SD_NODE_INIT for TILE architecture */ #define SD_NODE_INIT (struct sched_domain) { \ .min_interval = 8, \ .max_interval = 32, \ .min_interval = 16, \ .max_interval = 512, \ .busy_factor = 32, \ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ Loading @@ -55,14 +89,19 @@ static inline const struct cpumask *cpumask_of_node(int node) .idle_idx = 1, \ .newidle_idx = 2, \ .wake_idx = 1, \ .flags = SD_LOAD_BALANCE \ | SD_BALANCE_NEWIDLE \ | SD_BALANCE_EXEC \ | SD_BALANCE_FORK \ | SD_WAKE_AFFINE \ | SD_SERIALIZE, \ .flags = 1*SD_LOAD_BALANCE \ | 1*SD_BALANCE_NEWIDLE \ | 1*SD_BALANCE_EXEC \ | 1*SD_BALANCE_FORK \ | 0*SD_BALANCE_WAKE \ | 0*SD_WAKE_AFFINE \ | 0*SD_PREFER_LOCAL \ | 0*SD_SHARE_CPUPOWER \ | 0*SD_SHARE_PKG_RESOURCES \ | 1*SD_SERIALIZE \ , \ .last_balance = jiffies, \ .balance_interval = 1, \ .balance_interval = 128, \ } /* By definition, we create nodes based on online memory. */ Loading Loading
arch/tile/include/asm/topology.h +57 −18 Original line number Diff line number Diff line Loading @@ -44,10 +44,44 @@ static inline const struct cpumask *cpumask_of_node(int node) /* For now, use numa node -1 for global allocation. */ #define pcibus_to_node(bus) ((void)(bus), -1) /* * TILE architecture has many cores integrated in one processor, so we need * setup bigger balance_interval for both CPU/NODE scheduling domains to * reduce process scheduling costs. */ /* sched_domains SD_CPU_INIT for TILE architecture */ #define SD_CPU_INIT (struct sched_domain) { \ .min_interval = 4, \ .max_interval = 128, \ .busy_factor = 64, \ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ .busy_idx = 2, \ .idle_idx = 1, \ .newidle_idx = 0, \ .wake_idx = 0, \ .forkexec_idx = 0, \ \ .flags = 1*SD_LOAD_BALANCE \ | 1*SD_BALANCE_NEWIDLE \ | 1*SD_BALANCE_EXEC \ | 1*SD_BALANCE_FORK \ | 0*SD_BALANCE_WAKE \ | 0*SD_WAKE_AFFINE \ | 0*SD_PREFER_LOCAL \ | 0*SD_SHARE_CPUPOWER \ | 0*SD_SHARE_PKG_RESOURCES \ | 0*SD_SERIALIZE \ , \ .last_balance = jiffies, \ .balance_interval = 32, \ } /* sched_domains SD_NODE_INIT for TILE architecture */ #define SD_NODE_INIT (struct sched_domain) { \ .min_interval = 8, \ .max_interval = 32, \ .min_interval = 16, \ .max_interval = 512, \ .busy_factor = 32, \ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ Loading @@ -55,14 +89,19 @@ static inline const struct cpumask *cpumask_of_node(int node) .idle_idx = 1, \ .newidle_idx = 2, \ .wake_idx = 1, \ .flags = SD_LOAD_BALANCE \ | SD_BALANCE_NEWIDLE \ | SD_BALANCE_EXEC \ | SD_BALANCE_FORK \ | SD_WAKE_AFFINE \ | SD_SERIALIZE, \ .flags = 1*SD_LOAD_BALANCE \ | 1*SD_BALANCE_NEWIDLE \ | 1*SD_BALANCE_EXEC \ | 1*SD_BALANCE_FORK \ | 0*SD_BALANCE_WAKE \ | 0*SD_WAKE_AFFINE \ | 0*SD_PREFER_LOCAL \ | 0*SD_SHARE_CPUPOWER \ | 0*SD_SHARE_PKG_RESOURCES \ | 1*SD_SERIALIZE \ , \ .last_balance = jiffies, \ .balance_interval = 1, \ .balance_interval = 128, \ } /* By definition, we create nodes based on online memory. */ Loading