Commit 714d2dc1 authored by Peter Chubb's avatar Peter Chubb Committed by Tony Luck
Browse files

[IA64] Allow /proc/pal/cpu0/vm_info under the simulator 



Not all of the PAL VM calls are implemented for the SKI simulator.
Don't just give up if one fails, print information from the calls
that succeed.

Signed-off-by: default avatarPeter Chubb <peterc@gelato.unsw.edu.au>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent dc90e95f

arch/ia64/kernel/palinfo.c

+60 −55
Original line number Diff line number Diff line
@@ -307,9 +307,7 @@ vm_info(char *page) 


	if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {

		printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);

		return 0;

	}



	} else {



		p += sprintf(p,

		     "Physical Address Space         : %d bits\n"
@@ -319,13 +317,14 @@ vm_info(char *page) 
		     "Hash Tag ID                    : 0x%x\n"

		     "Size of RR.rid                 : %d\n",

		     vm_info_1.pal_vm_info_1_s.phys_add_size,

		     vm_info_2.pal_vm_info_2_s.impl_va_msb+1, vm_info_1.pal_vm_info_1_s.max_pkr+1,

		     vm_info_1.pal_vm_info_1_s.key_size, vm_info_1.pal_vm_info_1_s.hash_tag_id,

		     vm_info_2.pal_vm_info_2_s.impl_va_msb+1,

		     vm_info_1.pal_vm_info_1_s.max_pkr+1,

		     vm_info_1.pal_vm_info_1_s.key_size,

		     vm_info_1.pal_vm_info_1_s.hash_tag_id,

		     vm_info_2.pal_vm_info_2_s.rid_size);

	}



	if (ia64_pal_mem_attrib(&attrib) != 0)

		return 0;



	if (ia64_pal_mem_attrib(&attrib) == 0) {

		p += sprintf(p, "Supported memory attributes    : ");

		sep = "";

		for (i = 0; i < 8; i++) {
@@ -335,11 +334,11 @@ vm_info(char *page) 
			}

		}

		p += sprintf(p, "\n");

	}



	if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {

		printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status);

		return 0;

	}

	} else {



		p += sprintf(p,

			     "\nTLB walker                     : %simplemented\n"
@@ -356,19 +355,18 @@ vm_info(char *page) 
		p += sprintf(p, "\nTLB purgeable page sizes       : ");



		p = bitvector_process(p, vw_pages);



	}

	if ((status=ia64_get_ptce(&ptce)) != 0) {

		printk(KERN_ERR "ia64_get_ptce=%ld\n", status);

		return 0;

	}



	} else {

		p += sprintf(p,

		     "\nPurge base address             : 0x%016lx\n"

		     "Purge outer loop count         : %d\n"

		     "Purge inner loop count         : %d\n"

		     "Purge outer loop stride        : %d\n"

		     "Purge inner loop stride        : %d\n",

		     ptce.base, ptce.count[0], ptce.count[1], ptce.stride[0], ptce.stride[1]);

		     ptce.base, ptce.count[0], ptce.count[1],

		     ptce.stride[0], ptce.stride[1]);



		p += sprintf(p,

		     "TC Levels                      : %d\n"
@@ -392,19 +390,26 @@ vm_info(char *page) 
				     "\tAssociativity       : %d\n"

				     "\tNumber of entries   : %d\n"

				     "\tFlags               : ",

				     cache_types[j+tc_info.tc_unified], i+1, tc_info.tc_num_sets,

				     tc_info.tc_associativity, tc_info.tc_num_entries);



			if (tc_info.tc_pf) p += sprintf(p, "PreferredPageSizeOptimized ");

			if (tc_info.tc_unified) p += sprintf(p, "Unified ");

			if (tc_info.tc_reduce_tr) p += sprintf(p, "TCReduction");

				     cache_types[j+tc_info.tc_unified], i+1,

				     tc_info.tc_num_sets,

				     tc_info.tc_associativity,

				     tc_info.tc_num_entries);



				if (tc_info.tc_pf)

					p += sprintf(p, "PreferredPageSizeOptimized ");

				if (tc_info.tc_unified)

					p += sprintf(p, "Unified ");

				if (tc_info.tc_reduce_tr)

					p += sprintf(p, "TCReduction");



				p += sprintf(p, "\n\tSupported page sizes: ");



				p = bitvector_process(p, tc_pages);



				/* when unified date (j=2) is enough */

			if (tc_info.tc_unified) break;

				if (tc_info.tc_unified)

					break;

			}

		}

	}

	p += sprintf(p, "\n");
@@ -440,14 +445,14 @@ register_info(char *page) 
		p += sprintf(p, "\n");

	}



	if (ia64_pal_rse_info(&phys_stacked, &hints) != 0) return 0;

	if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) {



	p += sprintf(p,

		     "RSE stacked physical registers   : %ld\n"

		     "RSE load/store hints             : %ld (%s)\n",

		     phys_stacked, hints.ph_data,

		     hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");



	}

	if (ia64_pal_debug_info(&iregs, &dregs))

		return 0;