Commit 7124b34f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-evk: Align pin configuration group names with schema 



Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

  ... 'usdhc3grp-100mhz', 'usdhc3grp-200mhz' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0f4c40f1

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

+6 −6
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ 
		>;

	};



	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41

		>;
@@ -182,7 +182,7 @@ 
		>;

	};



	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194

			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
@@ -194,7 +194,7 @@ 
		>;

	};



	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196

			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
@@ -206,7 +206,7 @@ 
		>;

	};



	pinctrl_usdhc2_gpio: usdhc2grp-gpio {

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4

		>;
@@ -228,7 +228,7 @@ 
		>;

	};



	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194

			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
@@ -244,7 +244,7 @@ 
		>;

	};



	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196

			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6