Commit 71193c46 authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8192 imp i2c wrapper clock support 



Add MT8192 imp i2c wrapper clock provider

Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-14-chun-jie.chen@mediatek.com


Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 014a4881

drivers/clk/mediatek/Kconfig

+6 −0
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@@ -526,6 +526,12 @@ config COMMON_CLK_MT8192_IMGSYS 
	help

	  This driver supports MediaTek MT8192 imgsys and imgsys2 clocks.



config COMMON_CLK_MT8192_IMP_IIC_WRAP

	bool "Clock driver for MediaTek MT8192 imp_iic_wrap"

	depends on COMMON_CLK_MT8192

	help

	  This driver supports MediaTek MT8192 imp_iic_wrap clocks.



config COMMON_CLK_MT8516

	bool "Clock driver for MediaTek MT8516"

	depends on ARCH_MEDIATEK || COMPILE_TEST

drivers/clk/mediatek/Makefile

+1 −0
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@@ -71,5 +71,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o 
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o

obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o

obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP) += clk-mt8192-imp_iic_wrap.o

obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o

obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o

drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c

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+119 −0
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// SPDX-License-Identifier: GPL-2.0-only

//

// Copyright (c) 2021 MediaTek Inc.

// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>



#include <linux/clk-provider.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mt8192-clk.h>



static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {

	.set_ofs = 0xe08,

	.clr_ofs = 0xe04,

	.sta_ofs = 0xe00,

};



#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift)			\

	GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift,	\

		&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)



static const struct mtk_gate imp_iic_wrap_c_clks[] = {

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C11, "imp_iic_wrap_c_i2c11", "infra_i2c0", 1),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C12, "imp_iic_wrap_c_i2c12", "infra_i2c0", 2),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C13, "imp_iic_wrap_c_i2c13", "infra_i2c0", 3),

};



static const struct mtk_gate imp_iic_wrap_e_clks[] = {

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0),

};



static const struct mtk_gate imp_iic_wrap_n_clks[] = {

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C0, "imp_iic_wrap_n_i2c0", "infra_i2c0", 0),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C6, "imp_iic_wrap_n_i2c6", "infra_i2c0", 1),

};



static const struct mtk_gate imp_iic_wrap_s_clks[] = {

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "infra_i2c0", 0),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C8, "imp_iic_wrap_s_i2c8", "infra_i2c0", 1),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C9, "imp_iic_wrap_s_i2c9", "infra_i2c0", 2),

};



static const struct mtk_gate imp_iic_wrap_w_clks[] = {

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0),

};



static const struct mtk_gate imp_iic_wrap_ws_clks[] = {

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C1, "imp_iic_wrap_ws_i2c1", "infra_i2c0", 0),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C2, "imp_iic_wrap_ws_i2c2", "infra_i2c0", 1),

	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C4, "imp_iic_wrap_ws_i2c4", "infra_i2c0", 2),

};



static const struct mtk_clk_desc imp_iic_wrap_c_desc = {

	.clks = imp_iic_wrap_c_clks,

	.num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),

};



static const struct mtk_clk_desc imp_iic_wrap_e_desc = {

	.clks = imp_iic_wrap_e_clks,

	.num_clks = ARRAY_SIZE(imp_iic_wrap_e_clks),

};



static const struct mtk_clk_desc imp_iic_wrap_n_desc = {

	.clks = imp_iic_wrap_n_clks,

	.num_clks = ARRAY_SIZE(imp_iic_wrap_n_clks),

};



static const struct mtk_clk_desc imp_iic_wrap_s_desc = {

	.clks = imp_iic_wrap_s_clks,

	.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),

};



static const struct mtk_clk_desc imp_iic_wrap_w_desc = {

	.clks = imp_iic_wrap_w_clks,

	.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),

};



static const struct mtk_clk_desc imp_iic_wrap_ws_desc = {

	.clks = imp_iic_wrap_ws_clks,

	.num_clks = ARRAY_SIZE(imp_iic_wrap_ws_clks),

};



static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap[] = {

	{

		.compatible = "mediatek,mt8192-imp_iic_wrap_c",

		.data = &imp_iic_wrap_c_desc,

	}, {

		.compatible = "mediatek,mt8192-imp_iic_wrap_e",

		.data = &imp_iic_wrap_e_desc,

	}, {

		.compatible = "mediatek,mt8192-imp_iic_wrap_n",

		.data = &imp_iic_wrap_n_desc,

	}, {

		.compatible = "mediatek,mt8192-imp_iic_wrap_s",

		.data = &imp_iic_wrap_s_desc,

	}, {

		.compatible = "mediatek,mt8192-imp_iic_wrap_w",

		.data = &imp_iic_wrap_w_desc,

	}, {

		.compatible = "mediatek,mt8192-imp_iic_wrap_ws",

		.data = &imp_iic_wrap_ws_desc,

	}, {

		/* sentinel */

	}

};



static struct platform_driver clk_mt8192_imp_iic_wrap_drv = {

	.probe = mtk_clk_simple_probe,

	.driver = {

		.name = "clk-mt8192-imp_iic_wrap",

		.of_match_table = of_match_clk_mt8192_imp_iic_wrap,

	},

};



builtin_platform_driver(clk_mt8192_imp_iic_wrap_drv);