Commit 710573de authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8192 basic clocks support 



Add MT8192 basic clock providers, include topckgen, apmixedsys,
infracfg and pericfg.

Signed-off-by: default avatarWeiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-10-chun-jie.chen@mediatek.com


Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent c58cd0e4

drivers/clk/mediatek/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -500,6 +500,14 @@ config COMMON_CLK_MT8183_VENCSYS 
	help

	  This driver supports MediaTek MT8183 vencsys clocks.



config COMMON_CLK_MT8192

	bool "Clock driver for MediaTek MT8192"

	depends on ARM64 || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARM64

	help

	  This driver supports MediaTek MT8192 basic clocks.



config COMMON_CLK_MT8516

	bool "Clock driver for MediaTek MT8516"

	depends on ARCH_MEDIATEK || COMPILE_TEST

drivers/clk/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -67,5 +67,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o 
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o

obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o

obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o

obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o

obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o

obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o

drivers/clk/mediatek/clk-mt8192.c

0 → 100644
+1326 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/mediatek/clk-mux.c

+7 −2
Original line number Diff line number Diff line
@@ -116,7 +116,12 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) 
	return 0;

}



static const struct clk_ops mtk_mux_ops = {

const struct clk_ops mtk_mux_clr_set_upd_ops = {

	.get_parent = mtk_clk_mux_get_parent,

	.set_parent = mtk_clk_mux_set_parent_setclr_lock,

};



const struct clk_ops mtk_mux_gate_clr_set_upd_ops  = {

	.enable = mtk_clk_mux_enable_setclr,

	.disable = mtk_clk_mux_disable_setclr,

	.is_enabled = mtk_clk_mux_is_enabled,
@@ -140,7 +145,7 @@ static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, 
	init.flags = mux->flags | CLK_SET_RATE_PARENT;

	init.parent_names = mux->parent_names;

	init.num_parents = mux->num_parents;

	init.ops = &mtk_mux_ops;

	init.ops = mux->ops;



	clk_mux->regmap = regmap;

	clk_mux->data = mux;

drivers/clk/mediatek/clk-mux.h

+16 −2
Original line number Diff line number Diff line
@@ -33,12 +33,13 @@ struct mtk_mux { 
	u8 gate_shift;

	s8 upd_shift;



	const struct clk_ops *ops;

	signed char num_parents;

};



#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,		\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd, _flags) {		\

			_gate, _upd_ofs, _upd, _flags, _ops) {		\

		.id = _id,						\

		.name = _name,						\

		.mux_ofs = _mux_ofs,					\
@@ -52,14 +53,19 @@ struct mtk_mux { 
		.parent_names = _parents,				\

		.num_parents = ARRAY_SIZE(_parents),			\

		.flags = _flags,					\

		.ops = &_ops,						\

	}



extern const struct clk_ops mtk_mux_clr_set_upd_ops;

extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;



#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd, _flags)			\

		GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_gate, _upd_ofs, _upd, _flags)			\

			_gate, _upd_ofs, _upd, _flags,			\

			mtk_mux_gate_clr_set_upd_ops)



#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,		\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\
@@ -69,6 +75,14 @@ struct mtk_mux { 
			_width, _gate, _upd_ofs, _upd,			\

			CLK_SET_RATE_PARENT)



#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,			\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			_upd_ofs, _upd)					\

		GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,	\

			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\

			0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,		\

			mtk_mux_clr_set_upd_ops)



int mtk_clk_register_muxes(const struct mtk_mux *muxes,

			   int num, struct device_node *node,

			   spinlock_t *lock,