Commit 70f83220 authored by Yifeng Zhao's avatar Yifeng Zhao Committed by Ulf Hansson
Browse files

mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs 



The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. Resetting the complete SDHCI controller through
the reset controller fixes the issue.

Signed-off-by: default avatarYifeng Zhao <yifeng.zhao@rock-chips.com>
[rebase, use optional variant of reset getter]
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 32346491

drivers/mmc/host/sdhci-of-dwcmshc.c

+25 −1
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/reset.h>

#include <linux/sizes.h>



#include "sdhci-pltfm.h"
@@ -63,6 +64,7 @@ 
struct rk3568_priv {

	/* Rockchip specified optional clocks */

	struct clk_bulk_data rockchip_clks[RK3568_MAX_CLKS];

	struct reset_control *reset;

	u8 txclk_tapnum;

};
@@ -255,6 +257,21 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock 
	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);

}



static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)

{

	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);

	struct rk35xx_priv *priv = dwc_priv->priv;



	if (mask & SDHCI_RESET_ALL && priv->reset) {

		reset_control_assert(priv->reset);

		udelay(1);

		reset_control_deassert(priv->reset);

	}



	sdhci_reset(host, mask);

}



static const struct sdhci_ops sdhci_dwcmshc_ops = {

	.set_clock		= sdhci_set_clock,

	.set_bus_width		= sdhci_set_bus_width,
@@ -269,7 +286,7 @@ static const struct sdhci_ops sdhci_dwcmshc_rk3568_ops = { 
	.set_bus_width		= sdhci_set_bus_width,

	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,

	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,

	.reset			= sdhci_reset,

	.reset			= rk35xx_sdhci_reset,

	.adma_write_desc	= dwcmshc_adma_write_desc,

};
@@ -292,6 +309,13 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc 
	int err;

	struct rk3568_priv *priv = dwc_priv->priv;



	priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));

	if (IS_ERR(priv->reset)) {

		err = PTR_ERR(priv->reset);

		dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);

		return err;

	}



	priv->rockchip_clks[0].id = "axi";

	priv->rockchip_clks[1].id = "block";

	priv->rockchip_clks[2].id = "timer";