Commit 70eacf42 authored by Joakim Zhang's avatar Joakim Zhang Committed by Shawn Guo
Browse files

arm64: dts: imx8m: correct assigned clocks for FEC 



CLK_ENET_TIMER assigned clocks twice, should be a typo, correct to
CLK_ENET_PHY_REF clock.

Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 69c910d3

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -915,11 +915,12 @@ 
				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,

						  <&clk IMX8MM_CLK_ENET_TIMER>,

						  <&clk IMX8MM_CLK_ENET_REF>,

						  <&clk IMX8MM_CLK_ENET_TIMER>;

						  <&clk IMX8MM_CLK_ENET_PHY_REF>;

				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,

							 <&clk IMX8MM_SYS_PLL2_100M>,

							 <&clk IMX8MM_SYS_PLL2_125M>;

				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;

							 <&clk IMX8MM_SYS_PLL2_125M>,

							 <&clk IMX8MM_SYS_PLL2_50M>;

				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;

				fsl,num-tx-queues = <3>;

				fsl,num-rx-queues = <3>;

				status = "disabled";

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -913,11 +913,12 @@ 
				assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,

						  <&clk IMX8MN_CLK_ENET_TIMER>,

						  <&clk IMX8MN_CLK_ENET_REF>,

						  <&clk IMX8MN_CLK_ENET_TIMER>;

						  <&clk IMX8MN_CLK_ENET_PHY_REF>;

				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,

							 <&clk IMX8MN_SYS_PLL2_100M>,

							 <&clk IMX8MN_SYS_PLL2_125M>;

				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;

							 <&clk IMX8MN_SYS_PLL2_125M>,

							 <&clk IMX8MN_SYS_PLL2_50M>;

				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;

				fsl,num-tx-queues = <3>;

				fsl,num-rx-queues = <3>;

				status = "disabled";

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -768,11 +768,12 @@ 
				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,

						  <&clk IMX8MP_CLK_ENET_TIMER>,

						  <&clk IMX8MP_CLK_ENET_REF>,

						  <&clk IMX8MP_CLK_ENET_TIMER>;

						  <&clk IMX8MP_CLK_ENET_PHY_REF>;

				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,

							 <&clk IMX8MP_SYS_PLL2_100M>,

							 <&clk IMX8MP_SYS_PLL2_125M>;

				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;

							 <&clk IMX8MP_SYS_PLL2_125M>,

							 <&clk IMX8MP_SYS_PLL2_50M>;

				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;

				fsl,num-tx-queues = <3>;

				fsl,num-rx-queues = <3>;

				status = "disabled";