Commit 70a4af36 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add ethernet clock sources 



Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match
with the register description as mentioned in RZ/G2L HW manual (Rev.1.00).

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 7c5a2561

drivers/clk/renesas/r9a07g044-cpg.c

+18 −1
Original line number Diff line number Diff line
@@ -35,8 +35,10 @@ enum clk_ids { 
	CLK_PLL3_DIV4,

	CLK_PLL4,

	CLK_PLL5,

	CLK_PLL5_DIV2,

	CLK_PLL5_FOUT3,

	CLK_PLL5_250,

	CLK_PLL6,

	CLK_PLL6_250,

	CLK_P1_DIV2,



	/* Module Clocks */
@@ -53,6 +55,9 @@ static const struct clk_div_table dtable_1_32[] = { 
	{0, 0},

};



/* Mux clock tables */

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };



static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {

	/* External Clock Inputs */

	DEF_INPUT("extal", CLK_EXTAL),
@@ -64,6 +69,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),

	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),



	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),

	DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),



	DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),



	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),

	DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),

	DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
@@ -73,6 +83,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),



	DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),

	DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),



	/* Core output clk */

	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),

	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
@@ -84,6 +97,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),

	DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,

		DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),

	DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),

	DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,

		sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),

};



static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {

drivers/clk/renesas/rzg2l-cpg.h

+3 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 


#define CPG_PL2_DDIV		(0x204)

#define CPG_PL3A_DDIV		(0x208)

#define CPG_PL6_ETH_SSEL	(0x418)



/* n = 0/1/2 for PLL1/4/6 */

#define CPG_SAMPLL_CLK1(n)	(0x04 + (16 * n))
@@ -27,6 +28,8 @@ 
#define SEL_PLL_PACK(offset, bitpos, size) \

		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))



#define SEL_PLL6_2	SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)



/**

 * Definitions of CPG Core Clocks

 *