Commit 708283ab authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "New controller support and updates to drivers.

  New support:
   - Qualcomm SM6115 and QCM2290 dmaengine support
   - at_xdma support for microchip,sam9x7 controller

  Updates:
   - idxd updates for wq simplification and ats knob updates
   - fsl edma updates for v3 support
   - Xilinx AXI4-Stream control support
   - Yaml conversion for bcm dma binding"

* tag 'dmaengine-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (53 commits)
  dmaengine: fsl-edma: integrate v3 support
  dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string
  dmaengine: fsl-edma: move tcd into struct fsl_dma_chan
  dmaengine: fsl-edma: refactor chan_name setup and safety
  dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function
  dmaengine: fsl-edma: refactor using devm_clk_get_enabled
  dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs()
  dmaengine: fsl-edma: move common IRQ handler to common.c
  dmaengine: fsl-edma: Remove enum edma_version
  dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata
  dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c
  dmaengine: fsl-edma: fix build error when arch is s390
  dmaengine: idxd: Fix issues with PRS disable sysfs knob
  dmaengine: idxd: Allow ATS disable update only for configurable devices
  dmaengine: xilinx_dma: Program interrupt delay timeout
  dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase
  dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit
  dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
  dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
  dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
  ...
parents db906f0c 72f5801a

Documentation/ABI/stable/sysfs-driver-dma-idxd

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ What: /sys/bus/dsa/devices/dsa<m>/pasid_enabled 
Date:		Oct 27, 2020

KernelVersion:	5.11.0

Contact:	dmaengine@vger.kernel.org

Description:	To indicate if PASID (process address space identifier) is

Description:	To indicate if user PASID (process address space identifier) is

		enabled or not for this device.



What:           /sys/bus/dsa/devices/dsa<m>/state

Documentation/devicetree/bindings/dma/atmel-xdma.txt

+2 −1
Original line number Diff line number Diff line
@@ -3,7 +3,8 @@ 
* XDMA Controller

Required properties:

- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or

  "microchip,sama7g5-dma".

  "microchip,sama7g5-dma" or

  "microchip,sam9x7-dma", "atmel,sama5d4-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <1>, used to represent the number of integer cells in

Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt

deleted100644 → 0
+0 −83
Original line number Diff line number Diff line 
* BCM2835 DMA controller



The BCM2835 DMA controller has 16 channels in total.

Only the lower 13 channels have an associated IRQ.

Some arbitrary channels are used by the firmware

(1,3,6,7 in the current firmware version).

The channels 0,2 and 3 have special functionality

and should not be used by the driver.



Required properties:

- compatible: Should be "brcm,bcm2835-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain the DMA interrupts associated

		to the DMA channels in ascending order.

- interrupt-names: Should contain the names of the interrupt

		   in the form "dmaXX".

		   Use "dma-shared-all" for the common interrupt line

		   that is shared by all dma channels.

- #dma-cells: Must be <1>, the cell in the dmas property of the

		client device represents the DREQ number.

- brcm,dma-channel-mask: Bit mask representing the channels

			 not used by the firmware in ascending order,

			 i.e. first channel corresponds to LSB.



Example:



dma: dma@7e007000 {

	compatible = "brcm,bcm2835-dma";

	reg = <0x7e007000 0xf00>;

	interrupts = <1 16>,

		     <1 17>,

		     <1 18>,

		     <1 19>,

		     <1 20>,

		     <1 21>,

		     <1 22>,

		     <1 23>,

		     <1 24>,

		     <1 25>,

		     <1 26>,

		     /* dma channel 11-14 share one irq */

		     <1 27>,

		     <1 27>,

		     <1 27>,

		     <1 27>,

		     /* unused shared irq for all channels */

		     <1 28>;

	interrupt-names = "dma0",

			  "dma1",

			  "dma2",

			  "dma3",

			  "dma4",

			  "dma5",

			  "dma6",

			  "dma7",

			  "dma8",

			  "dma9",

			  "dma10",

			  "dma11",

			  "dma12",

			  "dma13",

			  "dma14",

			  "dma-shared-all";



	#dma-cells = <1>;

	brcm,dma-channel-mask = <0x7f35>;

};





DMA clients connected to the BCM2835 DMA controller must use the format

described in the dma.txt file, using a two-cell specifier for each channel.



Example:



bcm2835_i2s: i2s@7e203000 {

	compatible = "brcm,bcm2835-i2s";

	reg = <	0x7e203000 0x24>;

	clocks = <&clocks BCM2835_CLOCK_PCM>;



	dmas = <&dma 2>,

	       <&dma 3>;

	dma-names = "tx", "rx";

};

Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.yaml

0 → 100644
+102 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: BCM2835 DMA controller



maintainers:

  - Nicolas Saenz Julienne <nsaenz@kernel.org>



description:

  The BCM2835 DMA controller has 16 channels in total. Only the lower

  13 channels have an associated IRQ. Some arbitrary channels are used by the

  VideoCore firmware (1,3,6,7 in the current firmware version). The channels

  0, 2 and 3 have special functionality and should not be used by the driver.



allOf:

  - $ref: dma-controller.yaml#



properties:

  compatible:

    const: brcm,bcm2835-dma



  reg:

    maxItems: 1



  interrupts:

    description:

      Should contain the DMA interrupts associated to the DMA channels in

      ascending order.

    minItems: 1

    maxItems: 16



  interrupt-names:

    minItems: 1

    maxItems: 16



  '#dma-cells':

    description: The single cell represents the DREQ number.

    const: 1



  brcm,dma-channel-mask:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Bitmask of available DMA channels in ascending order that are

      not reserved by firmware and are available to the

      kernel. i.e. first channel corresponds to LSB.



unevaluatedProperties: false



required:

  - compatible

  - reg

  - interrupts

  - "#dma-cells"

  - brcm,dma-channel-mask



examples:

  - |

    dma-controller@7e007000 {

      compatible = "brcm,bcm2835-dma";

      reg = <0x7e007000 0xf00>;

      interrupts = <1 16>,

                   <1 17>,

                   <1 18>,

                   <1 19>,

                   <1 20>,

                   <1 21>,

                   <1 22>,

                   <1 23>,

                   <1 24>,

                   <1 25>,

                   <1 26>,

                   /* dma channel 11-14 share one irq */

                   <1 27>,

                   <1 27>,

                   <1 27>,

                   <1 27>,

                   /* unused shared irq for all channels */

                   <1 28>;

      interrupt-names = "dma0",

                        "dma1",

                        "dma2",

                        "dma3",

                        "dma4",

                        "dma5",

                        "dma6",

                        "dma7",

                        "dma8",

                        "dma9",

                        "dma10",

                        "dma11",

                        "dma12",

                        "dma13",

                        "dma14",

                        "dma-shared-all";

        #dma-cells = <1>;

        brcm,dma-channel-mask = <0x7f35>;

    };



...

Documentation/devicetree/bindings/dma/fsl,edma.yaml

+99 −7
Original line number Diff line number Diff line
@@ -21,32 +21,41 @@ properties: 
      - enum:

          - fsl,vf610-edma

          - fsl,imx7ulp-edma

          - fsl,imx8qm-adma

          - fsl,imx8qm-edma

          - fsl,imx93-edma3

          - fsl,imx93-edma4

      - items:

          - const: fsl,ls1028a-edma

          - const: fsl,vf610-edma



  reg:

    minItems: 2

    minItems: 1

    maxItems: 3



  interrupts:

    minItems: 2

    maxItems: 17

    minItems: 1

    maxItems: 64



  interrupt-names:

    minItems: 2

    maxItems: 17

    minItems: 1

    maxItems: 64



  "#dma-cells":

    const: 2

    enum:

      - 2

      - 3



  dma-channels:

    const: 32

    minItems: 1

    maxItems: 64



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    maxItems: 2



  big-endian:
@@ -65,6 +74,29 @@ required: 


allOf:

  - $ref: dma-controller.yaml#

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qm-adma

              - fsl,imx8qm-edma

              - fsl,imx93-edma3

              - fsl,imx93-edma4

    then:

      properties:

        "#dma-cells":

          const: 3

        # It is not necessary to write the interrupt name for each channel.

        # instead, you can simply maintain the sequential IRQ numbers as

        # defined for the DMA channels.

        interrupt-names: false

        clock-names:

          items:

            - const: dma

        clocks:

          maxItems: 1



  - if:

      properties:

        compatible:
@@ -72,18 +104,26 @@ allOf: 
            const: fsl,vf610-edma

    then:

      properties:

        clocks:

          minItems: 2

        clock-names:

          items:

            - const: dmamux0

            - const: dmamux1

        interrupts:

          minItems: 2

          maxItems: 2

        interrupt-names:

          items:

            - const: edma-tx

            - const: edma-err

        reg:

          minItems: 2

          maxItems: 3

        "#dma-cells":

          const: 2

        dma-channels:

          const: 32



  - if:

      properties:
@@ -92,14 +132,22 @@ allOf: 
            const: fsl,imx7ulp-edma

    then:

      properties:

        clock:

          minItems: 2

        clock-names:

          items:

            - const: dma

            - const: dmamux0

        interrupts:

          minItems: 2

          maxItems: 17

        reg:

          minItems: 2

          maxItems: 2

        "#dma-cells":

          const: 2

        dma-channels:

          const: 32



unevaluatedProperties: false
@@ -153,3 +201,47 @@ examples: 
       clock-names = "dma", "dmamux0";

       clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;

    };



  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/imx93-clock.h>



    dma-controller@44000000 {

      compatible = "fsl,imx93-edma3";

      reg = <0x44000000 0x200000>;

      #dma-cells = <3>;

      dma-channels = <31>;

      interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk IMX93_CLK_EDMA1_GATE>;

        clock-names = "dma";

    };