Commit 707116b6 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-ethernet-mtk_eth_soc-add-basic-support-for-mt7988-soc' 

Daniel Golle says:

====================
net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC

The MediaTek MT7988 SoC introduces a new version (3) of the NETSYS
block and comes with three instead of two MACs.

The first MAC can be internally connected to a built-in Gigabit
Ethernet switch with four 1000M/100M/10M twisted pair user ports.

The second MAC can be internally connected to a built-in 2500Base-T
Ethernet PHY.

There are two SerDes units which can be operated in USXGMII, 10GBase-(K)R,
5GBase-R, 2500Base-X, 1000Base-X or SGMII interface mode.

This series adds initial support for NETSYS v3 and the first MAC of the
MT7988 SoC connecting the built-in DSA switch.

The switch is supported since commit 110c18bf ("net: dsa: mt7530:
introduce driver for MT7988 built-in switch").

Basic support for the 1000M/100M/10M built-in PHYs connected to the
switch ports is present since commit ("98c485ea net: phy: add
driver for MediaTek SoC built-in GE PHYs").
====================

Link: https://lore.kernel.org/r/cover.1690246066.git.daniel@makrotopia.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents ac3cb6de 445eb644

Documentation/devicetree/bindings/net/mediatek,net.yaml

+102 −7
Original line number Diff line number Diff line
@@ -19,10 +19,12 @@ properties: 
    enum:

      - mediatek,mt2701-eth

      - mediatek,mt7623-eth

      - mediatek,mt7621-eth

      - mediatek,mt7622-eth

      - mediatek,mt7629-eth

      - mediatek,mt7981-eth

      - mediatek,mt7986-eth

      - mediatek,mt7988-eth

      - ralink,rt5350-eth



  reg:
@@ -32,7 +34,7 @@ properties: 
  clock-names: true



  interrupts:

    minItems: 3

    minItems: 1

    maxItems: 4



  power-domains:
@@ -60,6 +62,12 @@ properties: 
      Phandle to the mediatek hifsys controller used to provide various clocks

      and reset to the system.



  mediatek,infracfg:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon node that handles the path from GMAC to

      PHY variants.



  mediatek,sgmiisys:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    minItems: 1
@@ -121,6 +129,8 @@ allOf: 
            - const: gp1

            - const: gp2



        mediatek,infracfg: false



        mediatek,pctl:

          $ref: /schemas/types.yaml#/definitions/phandle

          description:
@@ -131,6 +141,32 @@ allOf: 


        mediatek,wed-pcie: false



  - if:

      properties:

        compatible:

          contains:

            enum:

              - mediatek,mt7621-eth

    then:

      properties:

        interrupts:

          maxItems: 1



        clocks:

          minItems: 2

          maxItems: 2



        clock-names:

          items:

            - const: ethif

            - const: fe



        mediatek,infracfg: false



        mediatek,wed: false



        mediatek,wed-pcie: false



  - if:

      properties:

        compatible:
@@ -159,6 +195,8 @@ allOf: 
            - const: sgmii_ck

            - const: eth2pll



        mediatek,infracfg: false



        mediatek,sgmiisys:

          minItems: 1

          maxItems: 1
@@ -204,12 +242,6 @@ allOf: 
            - const: sgmii_ck

            - const: eth2pll



        mediatek,infracfg:

          $ref: /schemas/types.yaml#/definitions/phandle

          description:

            Phandle to the syscon node that handles the path from GMAC to

            PHY variants.



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2
@@ -250,6 +282,8 @@ allOf: 
            - const: netsys0

            - const: netsys1



        mediatek,infracfg: false



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2
@@ -286,6 +320,67 @@ allOf: 
            - const: netsys0

            - const: netsys1



        mediatek,infracfg: false



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2



  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt7988-eth

    then:

      properties:

        interrupts:

          minItems: 4



        clocks:

          minItems: 34

          maxItems: 34



        clock-names:

          items:

            - const: crypto

            - const: fe

            - const: gp2

            - const: gp1

            - const: gp3

            - const: ethwarp_wocpu2

            - const: ethwarp_wocpu1

            - const: ethwarp_wocpu0

            - const: esw

            - const: netsys0

            - const: netsys1

            - const: sgmii_tx250m

            - const: sgmii_rx250m

            - const: sgmii2_tx250m

            - const: sgmii2_rx250m

            - const: top_usxgmii0_sel

            - const: top_usxgmii1_sel

            - const: top_sgm0_sel

            - const: top_sgm1_sel

            - const: top_xfi_phy0_xtal_sel

            - const: top_xfi_phy1_xtal_sel

            - const: top_eth_gmii_sel

            - const: top_eth_refck_50m_sel

            - const: top_eth_sys_200m_sel

            - const: top_eth_sys_sel

            - const: top_eth_xgmii_sel

            - const: top_eth_mii_sel

            - const: top_netsys_sel

            - const: top_netsys_500m_sel

            - const: top_netsys_pao_2x_sel

            - const: top_netsys_sync_250m_sel

            - const: top_netsys_ppefb_250m_sel

            - const: top_netsys_warp_sel

            - const: wocpu1

            - const: wocpu0

            - const: xgp1

            - const: xgp2

            - const: xgp3



        mediatek,sgmiisys:

          minItems: 2

          maxItems: 2

drivers/net/ethernet/mediatek/mtk_eth_path.c

+19 −17
Original line number Diff line number Diff line
@@ -15,10 +15,10 @@ 
struct mtk_eth_muxc {

	const char	*name;

	int		cap_bit;

	int		(*set_path)(struct mtk_eth *eth, int path);

	int		(*set_path)(struct mtk_eth *eth, u64 path);

};



static const char *mtk_eth_path_name(int path)

static const char *mtk_eth_path_name(u64 path)

{

	switch (path) {

	case MTK_ETH_PATH_GMAC1_RGMII:
@@ -40,10 +40,10 @@ static const char *mtk_eth_path_name(int path) 
	}

}



static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path)

static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)

{

	bool updated = true;

	u32 val, mask, set;

	u32 mask, set, reg;



	switch (path) {

	case MTK_ETH_PATH_GMAC1_SGMII:
@@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path) 
		break;

	}



	if (updated) {

		val = mtk_r32(eth, MTK_MAC_MISC);

		val = (val & mask) | set;

		mtk_w32(eth, val, MTK_MAC_MISC);

	}

	if (mtk_is_netsys_v3_or_greater(eth))

		reg = MTK_MAC_MISC_V3;

	else

		reg = MTK_MAC_MISC;



	if (updated)

		mtk_m32(eth, mask, set, reg);



	dev_dbg(eth->dev, "path %s in %s updated = %d\n",

		mtk_eth_path_name(path), __func__, updated);
@@ -71,7 +73,7 @@ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path) 
	return 0;

}



static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path)

static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path)

{

	unsigned int val = 0;

	bool updated = true;
@@ -94,7 +96,7 @@ static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path) 
	return 0;

}



static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)

static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)

{

	unsigned int val = 0, mask = 0, reg = 0;

	bool updated = true;
@@ -125,7 +127,7 @@ static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path) 
	return 0;

}



static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path)

static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)

{

	unsigned int val = 0;

	bool updated = true;
@@ -163,7 +165,7 @@ static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path) 
	return 0;

}



static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path)

static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)

{

	unsigned int val = 0;

	bool updated = true;
@@ -218,7 +220,7 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = { 
	},

};



static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)

static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path)

{

	int i, err = 0;
@@ -249,7 +251,7 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, int path) 


int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)

{

	int path;

	u64 path;



	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_SGMII :

				MTK_ETH_PATH_GMAC2_SGMII;
@@ -260,7 +262,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) 


int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)

{

	int path = 0;

	u64 path = 0;



	if (mac_id == 1)

		path = MTK_ETH_PATH_GMAC2_GEPHY;
@@ -274,7 +276,7 @@ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) 


int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)

{

	int path;

	u64 path;



	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_RGMII :

				MTK_ETH_PATH_GMAC2_RGMII;

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+309 −89

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+226 −101
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
#define MTK_TX_DMA_BUF_LEN_V2	0xffff

#define MTK_QDMA_RING_SIZE	2048

#define MTK_DMA_SIZE		512

#define MTK_MAC_COUNT		2

#define MTK_RX_ETH_HLEN		(ETH_HLEN + ETH_FCS_LEN)

#define MTK_RX_HLEN		(NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)

#define MTK_DMA_DUMMY_DESC	0xffffffff
@@ -118,14 +117,21 @@ 
#define MTK_CDMP_EG_CTRL	0x404



/* GDM Exgress Control Register */

#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))

#define MTK_GDMA_FWD_CFG(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\

				   0x540 : 0x500 + (_x * 0x1000); })

#define MTK_GDMA_SPECIAL_TAG	BIT(24)

#define MTK_GDMA_ICS_EN		BIT(22)

#define MTK_GDMA_TCS_EN		BIT(21)

#define MTK_GDMA_UCS_EN		BIT(20)

#define MTK_GDMA_STRP_CRC	BIT(16)

#define MTK_GDMA_TO_PDMA	0x0

#define MTK_GDMA_DROP_ALL       0x7777



/* GDM Egress Control Register */

#define MTK_GDMA_EG_CTRL(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\

				   0x544 : 0x504 + (_x * 0x1000); })

#define MTK_GDMA_XGDM_SEL	BIT(31)



/* Unicast Filter MAC Address Register - Low */

#define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
@@ -288,8 +294,6 @@ 
/* QDMA Interrupt grouping registers */

#define MTK_RLS_DONE_INT	BIT(0)



#define MTK_STAT_OFFSET		0x40



/* QDMA TX NUM */

#define QID_BITS_V2(x)		(((x) & 0x3f) << 16)

#define MTK_QDMA_GMAC2_QID	8
@@ -302,6 +306,8 @@ 
#define TX_DMA_CHKSUM_V2	(0x7 << 28)

#define TX_DMA_TSO_V2		BIT(31)



#define TX_DMA_SPTAG_V3         BIT(27)



/* QDMA V2 descriptor txd4 */

#define TX_DMA_FPORT_SHIFT_V2	8

#define TX_DMA_FPORT_MASK_V2	0xf
@@ -389,7 +395,26 @@ 
#define PHY_IAC_TIMEOUT		HZ



#define MTK_MAC_MISC		0x1000c

#define MTK_MAC_MISC_V3		0x10010

#define MTK_MUX_TO_ESW		BIT(0)

#define MISC_MDC_TURBO		BIT(4)



/* XMAC status registers */

#define MTK_XGMAC_STS(x)	(((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)

#define MTK_XGMAC_FORCE_LINK(x)	(((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))

#define MTK_USXGMII_PCS_LINK	BIT(8)

#define MTK_XGMAC_RX_FC		BIT(5)

#define MTK_XGMAC_TX_FC		BIT(4)

#define MTK_USXGMII_PCS_MODE	GENMASK(3, 1)

#define MTK_XGMAC_LINK_STS	BIT(0)



/* GSW bridge registers */

#define MTK_GSW_CFG		(0x10080)

#define GSWTX_IPG_MASK		GENMASK(19, 16)

#define GSWTX_IPG_SHIFT		16

#define GSWRX_IPG_MASK		GENMASK(3, 0)

#define GSWRX_IPG_SHIFT		0

#define GSW_IPG_11		11



/* Mac control registers */

#define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
@@ -635,12 +660,6 @@ enum mtk_tx_flags { 
	 */

	MTK_TX_FLAGS_SINGLE0	= 0x01,

	MTK_TX_FLAGS_PAGE0	= 0x02,



	/* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted

	 * SKB out instead of looking up through hardware TX descriptor.

	 */

	MTK_TX_FLAGS_FPORT0	= 0x04,

	MTK_TX_FLAGS_FPORT1	= 0x08,

};



/* This enum allows us to identify how the clock is defined on the array of the
@@ -653,6 +672,11 @@ enum mtk_clks_map { 
	MTK_CLK_GP0,

	MTK_CLK_GP1,

	MTK_CLK_GP2,

	MTK_CLK_GP3,

	MTK_CLK_XGP1,

	MTK_CLK_XGP2,

	MTK_CLK_XGP3,

	MTK_CLK_CRYPTO,

	MTK_CLK_FE,

	MTK_CLK_TRGPLL,

	MTK_CLK_SGMII_TX_250M,
@@ -669,63 +693,145 @@ enum mtk_clks_map { 
	MTK_CLK_WOCPU1,

	MTK_CLK_NETSYS0,

	MTK_CLK_NETSYS1,

	MTK_CLK_ETHWARP_WOCPU2,

	MTK_CLK_ETHWARP_WOCPU1,

	MTK_CLK_ETHWARP_WOCPU0,

	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,

	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,

	MTK_CLK_TOP_SGM_0_SEL,

	MTK_CLK_TOP_SGM_1_SEL,

	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,

	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,

	MTK_CLK_TOP_ETH_GMII_SEL,

	MTK_CLK_TOP_ETH_REFCK_50M_SEL,

	MTK_CLK_TOP_ETH_SYS_200M_SEL,

	MTK_CLK_TOP_ETH_SYS_SEL,

	MTK_CLK_TOP_ETH_XGMII_SEL,

	MTK_CLK_TOP_ETH_MII_SEL,

	MTK_CLK_TOP_NETSYS_SEL,

	MTK_CLK_TOP_NETSYS_500M_SEL,

	MTK_CLK_TOP_NETSYS_PAO_2X_SEL,

	MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,

	MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,

	MTK_CLK_TOP_NETSYS_WARP_SEL,

	MTK_CLK_MAX

};



#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \

				 BIT(MTK_CLK_TRGPLL))

#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_GP2) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK) | \

				 BIT(MTK_CLK_ETH2PLL))

#define MT7623_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \

				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_TRGPLL))

#define MT7622_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \

				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII_CK) | \

				 BIT_ULL(MTK_CLK_ETH2PLL))

#define MT7621_CLKS_BITMAP	(0)

#define MT7628_CLKS_BITMAP	(0)

#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \

				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII2_TX_250M) | \

				 BIT(MTK_CLK_SGMII2_RX_250M) | \

				 BIT(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK) | \

				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))

#define MT7981_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_WOCPU0) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII2_TX_250M) | \

				 BIT(MTK_CLK_SGMII2_RX_250M) | \

				 BIT(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT(MTK_CLK_SGMII_CK))

#define MT7986_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \

				 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \

				 BIT(MTK_CLK_SGMII_TX_250M) | \

				 BIT(MTK_CLK_SGMII_RX_250M) | \

				 BIT(MTK_CLK_SGMII_CDR_REF) | \

				 BIT(MTK_CLK_SGMII_CDR_FB) | \

				 BIT(MTK_CLK_SGMII2_TX_250M) | \

				 BIT(MTK_CLK_SGMII2_RX_250M) | \

				 BIT(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT(MTK_CLK_SGMII2_CDR_FB))

#define MT7629_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \

				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII_CK) | \

				 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))

#define MT7981_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_WOCPU0) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII_CK))

#define MT7986_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_GP1) | \

				 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \

				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))

#define MT7988_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \

				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \

				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \

				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \

				 BIT_ULL(MTK_CLK_CRYPTO) | \

				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \

				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \

				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \

				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \

				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \

				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \

				 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))



enum mtk_dev_state {

	MTK_HW_INIT,

	MTK_RESETTING

};



/* PSE Port Definition */

enum mtk_pse_port {

	PSE_ADMA_PORT = 0,

	PSE_GDM1_PORT,

	PSE_GDM2_PORT,

	PSE_PPE0_PORT,

	PSE_PPE1_PORT,

	PSE_QDMA_TX_PORT,

	PSE_QDMA_RX_PORT,

	PSE_DROP_PORT,

	PSE_WDMA0_PORT,

	PSE_WDMA1_PORT,

	PSE_TDMA_PORT,

	PSE_NONE_PORT,

	PSE_PPE2_PORT,

	PSE_WDMA2_PORT,

	PSE_EIP197_PORT,

	PSE_GDM3_PORT,

	PSE_PORT_MAX

};



/* GMAC Identifier */

enum mtk_gmac_id {

	MTK_GMAC1_ID = 0,

	MTK_GMAC2_ID,

	MTK_GMAC3_ID,

	MTK_GMAC_ID_MAX

};



enum mtk_tx_buf_type {

	MTK_TYPE_SKB,

	MTK_TYPE_XDP_TX,
@@ -744,7 +850,8 @@ struct mtk_tx_buf { 
	enum mtk_tx_buf_type type;

	void *data;



	u32 flags;

	u16 mac_id;

	u16 flags;

	DEFINE_DMA_UNMAP_ADDR(dma_addr0);

	DEFINE_DMA_UNMAP_LEN(dma_len0);

	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
@@ -820,7 +927,6 @@ enum mkt_eth_capabilities { 
	MTK_SHARED_INT_BIT,

	MTK_TRGMII_MT7621_CLK_BIT,

	MTK_QDMA_BIT,

	MTK_NETSYS_V2_BIT,

	MTK_SOC_MT7628_BIT,

	MTK_RSTCTRL_PPE1_BIT,

	MTK_U3_COPHY_V2_BIT,
@@ -843,42 +949,41 @@ enum mkt_eth_capabilities { 
};



/* Supported hardware group on SoCs */

#define MTK_RGMII		BIT(MTK_RGMII_BIT)

#define MTK_TRGMII		BIT(MTK_TRGMII_BIT)

#define MTK_SGMII		BIT(MTK_SGMII_BIT)

#define MTK_ESW			BIT(MTK_ESW_BIT)

#define MTK_GEPHY		BIT(MTK_GEPHY_BIT)

#define MTK_MUX			BIT(MTK_MUX_BIT)

#define MTK_INFRA		BIT(MTK_INFRA_BIT)

#define MTK_SHARED_SGMII	BIT(MTK_SHARED_SGMII_BIT)

#define MTK_HWLRO		BIT(MTK_HWLRO_BIT)

#define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)

#define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)

#define MTK_QDMA		BIT(MTK_QDMA_BIT)

#define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)

#define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)

#define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)

#define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)

#define MTK_RGMII		BIT_ULL(MTK_RGMII_BIT)

#define MTK_TRGMII		BIT_ULL(MTK_TRGMII_BIT)

#define MTK_SGMII		BIT_ULL(MTK_SGMII_BIT)

#define MTK_ESW			BIT_ULL(MTK_ESW_BIT)

#define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)

#define MTK_MUX			BIT_ULL(MTK_MUX_BIT)

#define MTK_INFRA		BIT_ULL(MTK_INFRA_BIT)

#define MTK_SHARED_SGMII	BIT_ULL(MTK_SHARED_SGMII_BIT)

#define MTK_HWLRO		BIT_ULL(MTK_HWLRO_BIT)

#define MTK_SHARED_INT		BIT_ULL(MTK_SHARED_INT_BIT)

#define MTK_TRGMII_MT7621_CLK	BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)

#define MTK_QDMA		BIT_ULL(MTK_QDMA_BIT)

#define MTK_SOC_MT7628		BIT_ULL(MTK_SOC_MT7628_BIT)

#define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)

#define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)



#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\

	BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)

	BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)

#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY	\

	BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)

	BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)

#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\

	BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)

	BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)

#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII	\

	BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)

	BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)

#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII	\

	BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)

	BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)



/* Supported path present on SoCs */

#define MTK_ETH_PATH_GMAC1_RGMII	BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)

#define MTK_ETH_PATH_GMAC1_TRGMII	BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)

#define MTK_ETH_PATH_GMAC1_SGMII	BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)

#define MTK_ETH_PATH_GMAC2_RGMII	BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)

#define MTK_ETH_PATH_GMAC2_SGMII	BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)

#define MTK_ETH_PATH_GMAC2_GEPHY	BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)

#define MTK_ETH_PATH_GDM1_ESW		BIT(MTK_ETH_PATH_GDM1_ESW_BIT)

#define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)

#define MTK_ETH_PATH_GMAC1_TRGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)

#define MTK_ETH_PATH_GMAC1_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)

#define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)

#define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)

#define MTK_ETH_PATH_GMAC2_GEPHY	BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)

#define MTK_ETH_PATH_GDM1_ESW		BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)



#define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)

#define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -934,11 +1039,13 @@ enum mkt_eth_capabilities { 
#define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \

		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \

		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \

		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)

		      MTK_RSTCTRL_PPE1)



#define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \

		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \

		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)

		      MTK_RSTCTRL_PPE1)



#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)



struct mtk_tx_dma_desc_info {

	dma_addr_t	addr;
@@ -1009,6 +1116,7 @@ struct mtk_reg_map { 
 * @required_pctl		A bool value to show whether the SoC requires

 *				the extra setup for those pins used by GMAC.

 * @hash_offset			Flow table hash offset.

 * @version			SoC version.

 * @foe_entry_size		Foe table entry size.

 * @has_accounting		Bool indicating support for accounting of

 *				offloaded flows.
@@ -1022,11 +1130,12 @@ struct mtk_reg_map { 
struct mtk_soc_data {

	const struct mtk_reg_map *reg_map;

	u32             ana_rgc3;

	u32		caps;

	u32		required_clks;

	u64		caps;

	u64		required_clks;

	bool		required_pctl;

	u8		offload_version;

	u8		hash_offset;

	u8		version;

	u16		foe_entry_size;

	netdev_features_t hw_features;

	bool		has_accounting;
@@ -1043,8 +1152,8 @@ struct mtk_soc_data { 


#define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)



/* currently no SoC has more than 2 macs */

#define MTK_MAX_DEVS			2

/* currently no SoC has more than 3 macs */

#define MTK_MAX_DEVS	3



/* struct mtk_eth -	This is the main datasructure for holding the state

 *			of the driver
@@ -1183,6 +1292,21 @@ struct mtk_mac { 
/* the struct describing the SoC. these are declared in the soc_xyz.c files */

extern const struct of_device_id of_mtk_match[];



static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)

{

	return eth->soc->version == 1;

}



static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)

{

	return eth->soc->version > 1;

}



static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth)

{

	return eth->soc->version > 2;

}



static inline struct mtk_foe_entry *

mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)

{
@@ -1193,7 +1317,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 


static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return MTK_FOE_IB1_BIND_TIMESTAMP_V2;



	return MTK_FOE_IB1_BIND_TIMESTAMP;
@@ -1201,7 +1325,7 @@ static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 


static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return MTK_FOE_IB1_BIND_PPPOE_V2;



	return MTK_FOE_IB1_BIND_PPPOE;
@@ -1209,7 +1333,7 @@ static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 


static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return MTK_FOE_IB1_BIND_VLAN_TAG_V2;



	return MTK_FOE_IB1_BIND_VLAN_TAG;
@@ -1217,7 +1341,7 @@ static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 


static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;



	return MTK_FOE_IB1_BIND_VLAN_LAYER;
@@ -1225,7 +1349,7 @@ static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 


static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);



	return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
@@ -1233,7 +1357,7 @@ static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 


static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);



	return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
@@ -1241,7 +1365,7 @@ static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 


static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return MTK_FOE_IB1_PACKET_TYPE_V2;



	return MTK_FOE_IB1_PACKET_TYPE;
@@ -1249,7 +1373,7 @@ static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 


static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);



	return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
@@ -1257,7 +1381,7 @@ static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 


static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)

{

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(eth))

		return MTK_FOE_IB2_MULTICAST_V2;



	return MTK_FOE_IB2_MULTICAST;
@@ -1268,6 +1392,7 @@ void mtk_stats_update_mac(struct mtk_mac *mac); 


void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);

u32 mtk_r32(struct mtk_eth *eth, unsigned reg);

u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);



int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);

int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);

drivers/net/ethernet/mediatek/mtk_ppe.c

+9 −9
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ int mtk_foe_entry_prepare(struct mtk_eth *eth, struct mtk_foe_entry *entry, 


	memset(entry, 0, sizeof(*entry));



	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {

	if (mtk_is_netsys_v2_or_greater(eth)) {

		val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |

		      FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) |

		      FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
@@ -272,7 +272,7 @@ int mtk_foe_entry_set_pse_port(struct mtk_eth *eth, 
	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);

	u32 val = *ib2;



	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {

	if (mtk_is_netsys_v2_or_greater(eth)) {

		val &= ~MTK_FOE_IB2_DEST_PORT_V2;

		val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port);

	} else {
@@ -423,7 +423,7 @@ int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry, 
	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);

	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);



	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {

	if (mtk_is_netsys_v2_or_greater(eth)) {

		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;

		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |

			 MTK_FOE_IB2_WDMA_WINFO_V2;
@@ -447,7 +447,7 @@ int mtk_foe_entry_set_queue(struct mtk_eth *eth, struct mtk_foe_entry *entry, 
{

	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);



	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {

	if (mtk_is_netsys_v2_or_greater(eth)) {

		*ib2 &= ~MTK_FOE_IB2_QID_V2;

		*ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue);

		*ib2 |= MTK_FOE_IB2_PSE_QOS_V2;
@@ -603,7 +603,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, 
	struct mtk_foe_entry *hwe;

	u32 val;



	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {

	if (mtk_is_netsys_v2_or_greater(eth)) {

		entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;

		entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2,

					 timestamp);
@@ -619,7 +619,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, 
	hwe->ib1 = entry->ib1;



	if (ppe->accounting) {

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))

		if (mtk_is_netsys_v2_or_greater(eth))

			val = MTK_FOE_IB2_MIB_CNT_V2;

		else

			val = MTK_FOE_IB2_MIB_CNT;
@@ -979,7 +979,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) 
			 MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |

	      FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,

			 MTK_PPE_ENTRIES_SHIFT);

	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(ppe->eth))

		val |= MTK_PPE_TB_CFG_INFO_SEL;

	ppe_w32(ppe, MTK_PPE_TB_CFG, val);
@@ -995,7 +995,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) 
	      MTK_PPE_FLOW_CFG_IP4_NAPT |

	      MTK_PPE_FLOW_CFG_IP4_DSLITE |

	      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;

	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))

	if (mtk_is_netsys_v2_or_greater(ppe->eth))

		val |= MTK_PPE_MD_TOAP_BYP_CRSN0 |

		       MTK_PPE_MD_TOAP_BYP_CRSN1 |

		       MTK_PPE_MD_TOAP_BYP_CRSN2 |
@@ -1037,7 +1037,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe) 


	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);



	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) {

	if (mtk_is_netsys_v2_or_greater(ppe->eth)) {

		ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);

		ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);

	}