Commit 7066248c authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/mte' into for-next/core 

* for-next/mte:
  kasan: Extend KASAN mode kernel parameter
  arm64: mte: Add asymmetric mode support
  arm64: mte: CPU feature detection for Asymm MTE
  arm64: mte: Bitfield definitions for Asymm MTE
  kasan: Remove duplicate of kasan_flag_async
  arm64: kasan: mte: move GCR_EL1 switch to task switch when KASAN disabled
parents dc6bab18 2d27e585

Documentation/dev-tools/kasan.rst

+5 −2
Original line number Diff line number Diff line
@@ -194,14 +194,17 @@ additional boot parameters that allow disabling KASAN or controlling features: 


- ``kasan=off`` or ``=on`` controls whether KASAN is enabled (default: ``on``).



- ``kasan.mode=sync`` or ``=async`` controls whether KASAN is configured in

  synchronous or asynchronous mode of execution (default: ``sync``).

- ``kasan.mode=sync``, ``=async`` or ``=asymm`` controls whether KASAN

  is configured in synchronous, asynchronous or asymmetric mode of

  execution (default: ``sync``).

  Synchronous mode: a bad access is detected immediately when a tag

  check fault occurs.

  Asynchronous mode: a bad access detection is delayed. When a tag check

  fault occurs, the information is stored in hardware (in the TFSR_EL1

  register for arm64). The kernel periodically checks the hardware and

  only reports tag faults during these checks.

  Asymmetric mode: a bad access is detected synchronously on reads and

  asynchronously on writes.



- ``kasan.stacktrace=off`` or ``=on`` disables or enables alloc and free stack

  traces collection (default: ``on``).

arch/arm64/include/asm/memory.h

+1 −0
Original line number Diff line number Diff line
@@ -243,6 +243,7 @@ static inline const void *__tag_set(const void *addr, u8 tag) 
#ifdef CONFIG_KASAN_HW_TAGS

#define arch_enable_tagging_sync()		mte_enable_kernel_sync()

#define arch_enable_tagging_async()		mte_enable_kernel_async()

#define arch_enable_tagging_asymm()		mte_enable_kernel_asymm()

#define arch_force_async_tag_fault()		mte_check_tfsr_exit()

#define arch_get_random_tag()			mte_get_random_tag()

#define arch_get_mem_tag(addr)			mte_get_mem_tag(addr)

arch/arm64/include/asm/mte-kasan.h

+5 −0
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag, 


void mte_enable_kernel_sync(void);

void mte_enable_kernel_async(void);

void mte_enable_kernel_asymm(void);



#else /* CONFIG_ARM64_MTE */
@@ -161,6 +162,10 @@ static inline void mte_enable_kernel_async(void) 
{

}



static inline void mte_enable_kernel_asymm(void)

{

}



#endif /* CONFIG_ARM64_MTE */



#endif /* __ASSEMBLY__ */

arch/arm64/include/asm/mte.h

+4 −4
Original line number Diff line number Diff line
@@ -88,11 +88,11 @@ static inline int mte_ptrace_copy_tags(struct task_struct *child, 


#ifdef CONFIG_KASAN_HW_TAGS

/* Whether the MTE asynchronous mode is enabled. */

DECLARE_STATIC_KEY_FALSE(mte_async_mode);

DECLARE_STATIC_KEY_FALSE(mte_async_or_asymm_mode);



static inline bool system_uses_mte_async_mode(void)

static inline bool system_uses_mte_async_or_asymm_mode(void)

{

	return static_branch_unlikely(&mte_async_mode);

	return static_branch_unlikely(&mte_async_or_asymm_mode);

}



void mte_check_tfsr_el1(void);
@@ -121,7 +121,7 @@ static inline void mte_check_tfsr_exit(void) 
	mte_check_tfsr_el1();

}

#else

static inline bool system_uses_mte_async_mode(void)

static inline bool system_uses_mte_async_or_asymm_mode(void)

{

	return false;

}

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -626,6 +626,7 @@ 
#define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_ASYMM	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)

#define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)



#define SCTLR_ELx_ENIA_SHIFT	31
@@ -671,6 +672,7 @@ 
#define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_ASYMM	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)

#define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)



#define SCTLR_EL1_BT1		(BIT(36))
@@ -812,6 +814,7 @@ 
#define ID_AA64PFR1_MTE_NI		0x0

#define ID_AA64PFR1_MTE_EL0		0x1

#define ID_AA64PFR1_MTE			0x2

#define ID_AA64PFR1_MTE_ASYMM		0x3



/* id_aa64zfr0 */

#define ID_AA64ZFR0_F64MM_SHIFT		56