Commit 6fe6f68f authored by Karthikeyan Periyasamy's avatar Karthikeyan Periyasamy Committed by Kalle Valo
Browse files

ath11k: add hal support for QCN9074 



Define the hal ring address and ring meta descriptor mask for
QCN9074. Move the platform specific address to the ath11k_hw_regs.
Define tx_mesh_enable ops in ath11k_hw_ops since its accessing
platform specific TCL descriptor.

Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1

Signed-off-by: default avatarKarthikeyan Periyasamy <periyasa@codeaurora.org>
Signed-off-by: default avatarAnilkumar Kolli <akolli@codeaurora.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1612946530-28504-8-git-send-email-akolli@codeaurora.org
parent 480a7361

drivers/net/wireless/ath/ath11k/core.c

+17 −0
Original line number Diff line number Diff line
@@ -158,6 +158,23 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { 
		.max_radios = 1,

		.single_pdev_only = false,

		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,

		.hw_ops = &qcn9074_ops,

		.internal_sleep_clock = false,

		.regs = &qcn9074_regs,

		.rxdma1_enable = true,

		.num_rxmda_per_pdev = 1,

		.rx_mac_buf_ring = false,

		.vdev_start_delay = false,

		.htt_peer_map_v2 = true,

		.tcl_0_only = false,

		.interface_modes = BIT(NL80211_IFTYPE_STATION) |

					BIT(NL80211_IFTYPE_AP) |

					BIT(NL80211_IFTYPE_MESH_POINT),

		.supports_monitor = true,

		.supports_shadow_regs = false,

		.idle_ps = false,

		.cold_boot_calib = false,

		.supports_suspend = false,

	},

};

drivers/net/wireless/ath/ath11k/dp_tx.c

+1 −1
Original line number Diff line number Diff line
@@ -178,7 +178,7 @@ int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 
	}



	if (ieee80211_vif_is_mesh(arvif->vif))

		ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1);

		ti.enable_mesh = true;



	ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);

drivers/net/wireless/ath/ath11k/hal.c

+41 −55
Original line number Diff line number Diff line
@@ -89,17 +89,6 @@ static const struct hal_srng_config hw_srng_config_template[] = { 
		.entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2,

		.lmac_ring = false,

		.ring_dir = HAL_SRNG_DIR_SRC,

		.reg_start = {

			(HAL_SEQ_WCSS_UMAC_CE0_SRC_REG +

			 HAL_CE_DST_RING_BASE_LSB),

			HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP,

		},

		.reg_size = {

			(HAL_SEQ_WCSS_UMAC_CE1_SRC_REG -

			 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG),

			(HAL_SEQ_WCSS_UMAC_CE1_SRC_REG -

			 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG),

		},

		.max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE,

	},

	{ /* CE_DST */
@@ -108,17 +97,6 @@ static const struct hal_srng_config hw_srng_config_template[] = { 
		.entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2,

		.lmac_ring = false,

		.ring_dir = HAL_SRNG_DIR_SRC,

		.reg_start = {

			(HAL_SEQ_WCSS_UMAC_CE0_DST_REG +

			 HAL_CE_DST_RING_BASE_LSB),

			HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP,

		},

		.reg_size = {

			(HAL_SEQ_WCSS_UMAC_CE1_DST_REG -

			 HAL_SEQ_WCSS_UMAC_CE0_DST_REG),

			(HAL_SEQ_WCSS_UMAC_CE1_DST_REG -

			 HAL_SEQ_WCSS_UMAC_CE0_DST_REG),

		},

		.max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE,

	},

	{ /* CE_DST_STATUS */
@@ -127,18 +105,6 @@ static const struct hal_srng_config hw_srng_config_template[] = { 
		.entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2,

		.lmac_ring = false,

		.ring_dir = HAL_SRNG_DIR_DST,

		.reg_start = {

			(HAL_SEQ_WCSS_UMAC_CE0_DST_REG +

			 HAL_CE_DST_STATUS_RING_BASE_LSB),

			(HAL_SEQ_WCSS_UMAC_CE0_DST_REG +

			 HAL_CE_DST_STATUS_RING_HP),

		},

		.reg_size = {

			(HAL_SEQ_WCSS_UMAC_CE1_DST_REG -

			 HAL_SEQ_WCSS_UMAC_CE0_DST_REG),

			(HAL_SEQ_WCSS_UMAC_CE1_DST_REG -

			 HAL_SEQ_WCSS_UMAC_CE0_DST_REG),

		},

		.max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE,

	},

	{ /* WBM_IDLE_LINK */
@@ -147,11 +113,6 @@ static const struct hal_srng_config hw_srng_config_template[] = { 
		.entry_size = sizeof(struct hal_wbm_link_desc) >> 2,

		.lmac_ring = false,

		.ring_dir = HAL_SRNG_DIR_SRC,

		.reg_start = {

			(HAL_SEQ_WCSS_UMAC_WBM_REG +

			 HAL_WBM_IDLE_LINK_RING_BASE_LSB),

			(HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP),

		},

		.max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE,

	},

	{ /* SW2WBM_RELEASE */
@@ -160,11 +121,6 @@ static const struct hal_srng_config hw_srng_config_template[] = { 
		.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,

		.lmac_ring = false,

		.ring_dir = HAL_SRNG_DIR_SRC,

		.reg_start = {

			(HAL_SEQ_WCSS_UMAC_WBM_REG +

			 HAL_WBM_RELEASE_RING_BASE_LSB),

			(HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP),

		},

		.max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE,

	},

	{ /* WBM2SW_RELEASE */
@@ -173,16 +129,6 @@ static const struct hal_srng_config hw_srng_config_template[] = { 
		.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,

		.lmac_ring = false,

		.ring_dir = HAL_SRNG_DIR_DST,

		.reg_start = {

			(HAL_SEQ_WCSS_UMAC_WBM_REG +

			 HAL_WBM0_RELEASE_RING_BASE_LSB),

			(HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP),

		},

		.reg_size = {

			(HAL_WBM1_RELEASE_RING_BASE_LSB -

			 HAL_WBM0_RELEASE_RING_BASE_LSB),

			(HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP),

		},

		.max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE,

	},

	{ /* RXDMA_BUF */
@@ -955,7 +901,7 @@ void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 
	/* Enable the SRNG */

	ath11k_hif_write32(ab,

			   HAL_SEQ_WCSS_UMAC_WBM_REG +

			   HAL_WBM_IDLE_LINK_RING_MISC_ADDR, 0x40);

			   HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab), 0x40);

}



int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
@@ -1234,6 +1180,46 @@ static int ath11k_hal_srng_create_config(struct ath11k_base *ab) 
	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab);

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;



	s = &hal->srng_config[HAL_CE_SRC];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB;

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP;

	s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -

		HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);

	s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -

		HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);



	s = &hal->srng_config[HAL_CE_DST];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB;

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP;

	s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -

		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);

	s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -

		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);



	s = &hal->srng_config[HAL_CE_DST_STATUS];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +

		HAL_CE_DST_STATUS_RING_BASE_LSB;

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP;

	s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -

		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);

	s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -

		HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);



	s = &hal->srng_config[HAL_WBM_IDLE_LINK];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;



	s = &hal->srng_config[HAL_SW2WBM_RELEASE];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(ab);

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP;



	s = &hal->srng_config[HAL_WBM2SW_RELEASE];

	s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);

	s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;

	s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) -

		HAL_WBM0_RELEASE_RING_BASE_LSB(ab);

	s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP;



	return 0;

}

drivers/net/wireless/ath/ath11k/hal.h

+18 −9
Original line number Diff line number Diff line
@@ -42,10 +42,14 @@ struct ath11k_base; 
#define HAL_SEQ_WCSS_UMAC_OFFSET		0x00a00000

#define HAL_SEQ_WCSS_UMAC_REO_REG		0x00a38000

#define HAL_SEQ_WCSS_UMAC_TCL_REG		0x00a44000

#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG		0x00a00000

#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG		0x00a01000

#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG		0x00a02000

#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG		0x00a03000

#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)

#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)

#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)

#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \

		(ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)

#define HAL_SEQ_WCSS_UMAC_WBM_REG		0x00a34000



#define HAL_CE_WFSS_CE_REG_BASE			0x01b80000
@@ -201,8 +205,10 @@ struct ath11k_base; 
#define HAL_REO_STATUS_HP(ab)			ab->hw_params.regs->hal_reo_status_hp



/* WBM Idle R0 address */

#define HAL_WBM_IDLE_LINK_RING_BASE_LSB		0x00000860

#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR	0x00000870

#define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)

#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \

		(ab->hw_params.regs->hal_wbm_idle_link_ring_misc)

#define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR	0x00000048

#define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR		0x0000004c

#define HAL_WBM_SCATTERED_RING_BASE_LSB		0x00000058
@@ -217,14 +223,17 @@ struct ath11k_base; 
#define HAL_WBM_IDLE_LINK_RING_HP		0x000030b0



/* SW2WBM R0 release address */

#define HAL_WBM_RELEASE_RING_BASE_LSB		0x000001d8

#define HAL_WBM_RELEASE_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm_release_ring_base_lsb)



/* SW2WBM R2 release address */

#define HAL_WBM_RELEASE_RING_HP			0x00003018



/* WBM2SW R0 release address */

#define HAL_WBM0_RELEASE_RING_BASE_LSB		0x00000910

#define HAL_WBM1_RELEASE_RING_BASE_LSB		0x00000968

#define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm0_release_ring_base_lsb)

#define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \

		(ab->hw_params.regs->hal_wbm1_release_ring_base_lsb)



/* WBM2SW R2 release address */

#define HAL_WBM0_RELEASE_RING_HP		0x000030c0

drivers/net/wireless/ath/ath11k/hal_desc.h

+7 −6
Original line number Diff line number Diff line
@@ -951,7 +951,7 @@ struct hal_reo_flush_cache { 


#define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP		GENMASK(18, 0)

#define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID		BIT(19)

#define HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE	BIT(20)

#define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE	BIT(20)

#define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE		BIT(21)

#define HAL_TCL_DATA_CMD_INFO2_TID			GENMASK(25, 22)

#define HAL_TCL_DATA_CMD_INFO2_LMAC_ID			GENMASK(27, 26)
@@ -959,6 +959,7 @@ struct hal_reo_flush_cache { 
#define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX	GENMASK(5, 0)

#define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX		GENMASK(25, 6)

#define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM		GENMASK(29, 26)

#define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE	GENMASK(31, 30)



#define HAL_TCL_DATA_CMD_INFO4_RING_ID			GENMASK(27, 20)

#define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT		GENMASK(31, 28)