Commit 6fb03dd0 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: cpu-8996: fix PLL configuration sequence 



Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux)
before PLL configuration. Switch them to the ACD afterwards.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-11-dmitry.baryshkov@linaro.org
parent fa0bc05f

drivers/clk/qcom/clk-cpu-8996.c

+14 −0
Original line number Diff line number Diff line
@@ -432,13 +432,27 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, 
{

	int i, ret;



	/* Select GPLL0 for 300MHz for both clusters */

	regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc);

	regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc);



	/* Ensure write goes through before PLLs are reconfigured */

	udelay(5);



	clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);

	clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);

	clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);

	clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);



	/* Wait for PLL(s) to lock */

	udelay(50);



	qcom_cpu_clk_msm8996_acd_init(regmap);



	/* Switch clusters to use the ACD leg */

	regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2);

	regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2);



	for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) {

		ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);

		if (ret)