Commit 6fac824f authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Marc Zyngier
Browse files

irqchip/loongson-liointc: Use architecture register to get coreid 



fa84f893 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.

Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.

Fixes: fa84f893 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609175242.977-1-jiaxun.yang@flygoat.com
parent e3f056a7

drivers/irqchip/irq-loongson-liointc.c

+7 −1
Original line number Diff line number Diff line
@@ -39,6 +39,12 @@ 


#define LIOINTC_ERRATA_IRQ	10



#if defined(CONFIG_MIPS)

#define liointc_core_id get_ebase_cpunum()

#else

#define liointc_core_id get_csr_cpuid()

#endif



struct liointc_handler_data {

	struct liointc_priv	*priv;

	u32			parent_int_map;
@@ -57,7 +63,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) 
	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);

	struct irq_chip *chip = irq_desc_get_chip(desc);

	struct irq_chip_generic *gc = handler->priv->gc;

	int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;

	int core = liointc_core_id % LIOINTC_NUM_CORES;

	u32 pending;



	chained_irq_enter(chip, desc);