Commit 6f5adb35 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-fixes-5.18-3' of... 

Merge tag 'kvmarm-fixes-5.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 fixes for 5.18, take #3

- Correctly expose GICv3 support even if no irqchip is created
  so that userspace doesn't observe it changing pointlessly
  (fixing a regression with QEMU)

- Don't issue a hypercall to set the id-mapped vectors when
  protected mode is enabled (fix for pKVM in combination with
  CPUs affected by Spectre-v3a)
parents b28cb0cd 2e403167

arch/arm64/kvm/arm.c

+2 −1
Original line number Diff line number Diff line
@@ -1436,7 +1436,8 @@ static int kvm_init_vector_slots(void) 
	base = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs));

	kvm_init_vector_slot(base, HYP_VECTOR_SPECTRE_DIRECT);



	if (kvm_system_needs_idmapped_vectors() && !has_vhe()) {

	if (kvm_system_needs_idmapped_vectors() &&

	    !is_protected_kvm_enabled()) {

		err = create_hyp_exec_mappings(__pa_symbol(__bp_harden_hyp_vecs),

					       __BP_HARDEN_HYP_VECS_SZ, &base);

		if (err)

arch/arm64/kvm/sys_regs.c

+1 −2
Original line number Diff line number Diff line
@@ -1123,8 +1123,7 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, 
		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);

		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);

		if (irqchip_in_kernel(vcpu->kvm) &&

		    vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {

		if (kvm_vgic_global_state.type == VGIC_V3) {

			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);

			val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);

		}