Commit 6f451b60 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Add Renoir Hubbub (v2) 



Controls the display hw's interface to memory.

v2: rebase (Alex)

Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35b82ba8

drivers/gpu/drm/amd/display/dc/dcn21/Makefile

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#

# Makefile for DCN21.



DCN21 = dcn21_hubp.o

DCN21 = dcn21_hubp.o dcn21_hubbub.o



CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c

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+595 −0
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/*

* Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */

#include "dm_services.h"

#include "dcn20/dcn20_hubbub.h"

#include "dcn21_hubbub.h"

#include "reg_helper.h"



#define REG(reg)\

	hubbub1->regs->reg

#define DC_LOGGER \

	hubbub1->base.ctx->logger

#define CTX \

	hubbub1->base.ctx



#undef FN

#define FN(reg_name, field_name) \

	hubbub1->shifts->field_name, hubbub1->masks->field_name



#define REG(reg)\

	hubbub1->regs->reg



#define CTX \

	hubbub1->base.ctx



#undef FN

#define FN(reg_name, field_name) \

	hubbub1->shifts->field_name, hubbub1->masks->field_name



#ifdef NUM_VMID

#undef NUM_VMID

#endif

#define NUM_VMID 1



static uint32_t convert_and_clamp(

	uint32_t wm_ns,

	uint32_t refclk_mhz,

	uint32_t clamp_value)

{

	uint32_t ret_val = 0;

	ret_val = wm_ns * refclk_mhz;

	ret_val /= 1000;



	if (ret_val > clamp_value)

		ret_val = clamp_value;



	return ret_val;

}



void dcn21_dchvm_init(struct hubbub *hubbub)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);



	//Init DCHVM block

	REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);



	//Poll until RIOMMU_ACTIVE = 1

	//TODO: Figure out interval us and retry count

	REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);



	//Reflect the power status of DCHUBBUB

	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);



	//Start rIOMMU prefetching

	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);



	// Enable dynamic clock gating

	REG_UPDATE_4(DCHVM_CLK_CTRL,

					HVM_DISPCLK_R_GATE_DIS, 0,

					HVM_DISPCLK_G_GATE_DIS, 0,

					HVM_DCFCLK_R_GATE_DIS, 0,

					HVM_DCFCLK_G_GATE_DIS, 0);



	//Poll until HOSTVM_PREFETCH_DONE = 1

	//TODO: Figure out interval us and retry count

	REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);

}



static int hubbub21_init_dchub(struct hubbub *hubbub,

		struct dcn_hubbub_phys_addr_config *pa_config)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);



	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,

		FB_BASE, pa_config->system_aperture.fb_base);

	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,

			FB_TOP, pa_config->system_aperture.fb_top);

	REG_SET(DCN_VM_FB_OFFSET, 0,

			FB_OFFSET, pa_config->system_aperture.fb_offset);

	REG_SET(DCN_VM_AGP_BOT, 0,

			AGP_BOT, pa_config->system_aperture.agp_bot);

	REG_SET(DCN_VM_AGP_TOP, 0,

			AGP_TOP, pa_config->system_aperture.agp_top);

	REG_SET(DCN_VM_AGP_BASE, 0,

			AGP_BASE, pa_config->system_aperture.agp_base);



	dcn21_dchvm_init(hubbub);



	return NUM_VMID;

}



static void hubbub21_program_urgent_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);

	uint32_t prog_wm_value;



	/* Repeat for water mark set A, B, C and D. */

	/* clock state A */

	if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) {

		hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;

		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,

				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);



		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->a.urgent_ns, prog_wm_value);

	}



	/* determine the transfer time for a quantity of data for a particular requestor.*/

	if (safe_to_lower || watermarks->a.frac_urg_bw_flip

			> hubbub1->watermarks.a.frac_urg_bw_flip) {

		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);

	}



	if (safe_to_lower || watermarks->a.frac_urg_bw_nom

			> hubbub1->watermarks.a.frac_urg_bw_nom) {

		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);

	}



	/* clock state B */

	if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {

		hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns;

		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,

				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, prog_wm_value);



		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->b.urgent_ns, prog_wm_value);

	}



	/* determine the transfer time for a quantity of data for a particular requestor.*/

	if (safe_to_lower || watermarks->a.frac_urg_bw_flip

			> hubbub1->watermarks.a.frac_urg_bw_flip) {

		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->a.frac_urg_bw_flip);

	}



	if (safe_to_lower || watermarks->a.frac_urg_bw_nom

			> hubbub1->watermarks.a.frac_urg_bw_nom) {

		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom);

	}



	/* clock state C */

	if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {

		hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;

		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,

				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, prog_wm_value);



		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->c.urgent_ns, prog_wm_value);

	}



	/* determine the transfer time for a quantity of data for a particular requestor.*/

	if (safe_to_lower || watermarks->a.frac_urg_bw_flip

			> hubbub1->watermarks.a.frac_urg_bw_flip) {

		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->a.frac_urg_bw_flip);

	}



	if (safe_to_lower || watermarks->a.frac_urg_bw_nom

			> hubbub1->watermarks.a.frac_urg_bw_nom) {

		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom);

	}



	/* clock state D */

	if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {

		hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;

		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,

				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, prog_wm_value);



		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->d.urgent_ns, prog_wm_value);

	}



	/* determine the transfer time for a quantity of data for a particular requestor.*/

	if (safe_to_lower || watermarks->a.frac_urg_bw_flip

			> hubbub1->watermarks.a.frac_urg_bw_flip) {

		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->a.frac_urg_bw_flip);

	}



	if (safe_to_lower || watermarks->a.frac_urg_bw_nom

			> hubbub1->watermarks.a.frac_urg_bw_nom) {

		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;



		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,

				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom);

	}

}



static void hubbub21_program_stutter_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);

	uint32_t prog_wm_value;



	/* clock state A */

	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns

			> hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {

		hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =

				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,

				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);

	}



	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns

			> hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) {

		hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns =

				watermarks->a.cstate_pstate.cstate_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->a.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,

				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);

	}



	/* clock state B */

	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns

			> hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {

		hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =

				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,

				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);

	}



	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns

			> hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) {

		hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns =

				watermarks->b.cstate_pstate.cstate_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->b.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,

				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);

	}



	/* clock state C */

	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns

			> hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {

		hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =

				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,

				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);

	}



	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns

			> hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) {

		hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns =

				watermarks->c.cstate_pstate.cstate_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->c.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,

				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);

	}



	/* clock state D */

	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns

			> hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {

		hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =

				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,

				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);

	}



	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns

			> hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) {

		hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns =

				watermarks->d.cstate_pstate.cstate_exit_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->d.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,

				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);

	}

}



static void hubbub21_program_pstate_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);

	uint32_t prog_wm_value;



	/* clock state A */

	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns

			> hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) {

		hubbub1->watermarks.a.cstate_pstate.pstate_change_ns =

				watermarks->a.cstate_pstate.pstate_change_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->a.cstate_pstate.pstate_change_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,

				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"

			"HW register value = 0x%x\n\n",

			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);

	}



	/* clock state B */

	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns

			> hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) {

		hubbub1->watermarks.b.cstate_pstate.pstate_change_ns =

				watermarks->b.cstate_pstate.pstate_change_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->b.cstate_pstate.pstate_change_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,

				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"

			"HW register value = 0x%x\n\n",

			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);

	}



	/* clock state C */

	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns

			> hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) {

		hubbub1->watermarks.c.cstate_pstate.pstate_change_ns =

				watermarks->c.cstate_pstate.pstate_change_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->c.cstate_pstate.pstate_change_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,

				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"

			"HW register value = 0x%x\n\n",

			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);

	}



	/* clock state D */

	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns

			> hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) {

		hubbub1->watermarks.d.cstate_pstate.pstate_change_ns =

				watermarks->d.cstate_pstate.pstate_change_ns;

		prog_wm_value = convert_and_clamp(

				watermarks->d.cstate_pstate.pstate_change_ns,

				refclk_mhz, 0x1fffff);

		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,

				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value,

				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);

		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"

			"HW register value = 0x%x\n\n",

			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);

	}

}



void hubbub21_program_watermarks(

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz,

		bool safe_to_lower)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);



	hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);

	hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);

	hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);



	/*

	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.

	 * If the memory controller is fully utilized and the DCHub requestors are

	 * well ahead of their amortized schedule, then it is safe to prevent the next winner

	 * from being committed and sent to the fabric.

	 * The utilization of the memory controller is approximated by ensuring that

	 * the number of outstanding requests is greater than a threshold specified

	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,

	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.

	 *

	 * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF)

	 * to turn off it for now.

	 */

	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,

			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);

	REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF,

			DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);

	REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL,

			DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);



	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);

}



void hubbub21_wm_read_state(struct hubbub *hubbub,

		struct dcn_hubbub_wm *wm)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);

	struct dcn_hubbub_wm_set *s;



	memset(wm, 0, sizeof(struct dcn_hubbub_wm));



	s = &wm->sets[0];

	s->wm_set = 0;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,

			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);



	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,

			 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage);



	s = &wm->sets[1];

	s->wm_set = 1;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,

			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);



	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,

			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage);



	s = &wm->sets[2];

	s->wm_set = 2;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,

			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);



	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C,

			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage);



	s = &wm->sets[3];

	s->wm_set = 3;

	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,

			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,

			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);



	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,

			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);



	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D,

			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);

}





static const struct hubbub_funcs hubbub21_funcs = {

	.update_dchub = hubbub2_update_dchub,

	.init_dchub_sys_ctx = hubbub21_init_dchub,

	.init_vm_ctx = NULL,

	.dcc_support_swizzle = hubbub2_dcc_support_swizzle,

	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,

	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,

	.wm_read_state = hubbub21_wm_read_state,

	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,

	.program_watermarks = hubbub21_program_watermarks,

};



void hubbub21_construct(struct dcn20_hubbub *hubbub,

	struct dc_context *ctx,

	const struct dcn_hubbub_registers *hubbub_regs,

	const struct dcn_hubbub_shift *hubbub_shift,

	const struct dcn_hubbub_mask *hubbub_mask)

{

	hubbub->base.ctx = ctx;



	hubbub->base.funcs = &hubbub21_funcs;



	hubbub->regs = hubbub_regs;

	hubbub->shifts = hubbub_shift;

	hubbub->masks = hubbub_mask;



	hubbub->debug_test_index_pstate = 0xB;

}

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h

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