Commit 6f3562b3 authored by Jani Nikula's avatar Jani Nikula
Browse files

Merge drm/drm-next into drm-intel-next 



Backmerge to sync the DP MST atomic changes to drm-intel-next.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parents 3fecf93c 89b03aea

Documentation/devicetree/bindings/display/bridge/chipone,icn6211.yaml

+9 −0
Original line number Diff line number Diff line
@@ -24,6 +24,15 @@ properties: 
    maxItems: 1

    description: virtual channel number of a DSI peripheral



  clock-names:

    const: refclk



  clocks:

    maxItems: 1

    description: |

        Optional external clock connected to REF_CLK input.

        The clock rate must be in 10..154 MHz range.



  enable-gpios:

    description: Bridge EN pin, chip is reset when EN is low.

Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml

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@@ -14,6 +14,19 @@ properties: 
  compatible:

    const: chrontel,ch7033



  chrontel,byteswap:

    $ref: /schemas/types.yaml#/definitions/uint8

    enum:

      - 0  # BYTE_SWAP_RGB

      - 1  # BYTE_SWAP_RBG

      - 2  # BYTE_SWAP_GRB

      - 3  # BYTE_SWAP_GBR

      - 4  # BYTE_SWAP_BRG

      - 5  # BYTE_SWAP_BGR

    description: |

      Set the byteswap value of the bridge. This is optional and if not

      set value of BYTE_SWAP_BGR is used.



  reg:

    maxItems: 1

    description: I2C address of the device

Documentation/devicetree/bindings/display/ingenic,lcd.yaml

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@@ -17,6 +17,8 @@ properties: 
    enum:

      - ingenic,jz4740-lcd

      - ingenic,jz4725b-lcd

      - ingenic,jz4760-lcd

      - ingenic,jz4760b-lcd

      - ingenic,jz4770-lcd

      - ingenic,jz4780-lcd

Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml

0 → 100644
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Display Port Controller



maintainers:

  - Chun-Kuang Hu <chunkuang.hu@kernel.org>

  - Jitao shi <jitao.shi@mediatek.com>



description: |

  MediaTek DP and eDP are different hardwares and there are some features

  which are not supported for eDP. For example, audio is not supported for

  eDP. Therefore, we need to use two different compatibles to describe them.

  In addition, We just need to enable the power domain of DP, so the clock

  of DP is generated by itself and we are not using other PLL to generate

  clocks.



properties:

  compatible:

    enum:

      - mediatek,mt8195-dp-tx

      - mediatek,mt8195-edp-tx



  reg:

    maxItems: 1



  nvmem-cells:

    maxItems: 1

    description: efuse data for display port calibration



  nvmem-cell-names:

    const: dp_calibration_data



  power-domains:

    maxItems: 1



  interrupts:

    maxItems: 1



  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Input endpoint of the controller, usually dp_intf



      port@1:

        $ref: /schemas/graph.yaml#/$defs/port-base

        unevaluatedProperties: false

        description: Output endpoint of the controller

        properties:

          endpoint:

            $ref: /schemas/media/video-interfaces.yaml#

            unevaluatedProperties: false

            properties:

              data-lanes:

                description: |

                  number of lanes supported by the hardware.

                  The possible values:

                  0       - For 1 lane enabled in IP.

                  0 1     - For 2 lanes enabled in IP.

                  0 1 2 3 - For 4 lanes enabled in IP.

                minItems: 1

                maxItems: 4

            required:

              - data-lanes



    required:

      - port@0

      - port@1



  max-linkrate-mhz:

    enum: [ 1620, 2700, 5400, 8100 ]

    description: maximum link rate supported by the hardware.



required:

  - compatible

  - reg

  - interrupts

  - ports

  - max-linkrate-mhz



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/mt8195-power.h>

    dptx@1c600000 {

        compatible = "mediatek,mt8195-dp-tx";

        reg = <0x1c600000 0x8000>;

        power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;

        interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;

        max-linkrate-mhz = <8100>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                dptx_in: endpoint {

                    remote-endpoint = <&dp_intf0_out>;

                };

            };

            port@1 {

                reg = <1>;

                dptx_out: endpoint {

                    data-lanes = <0 1 2 3>;

                };

            };

        };

    };

Documentation/devicetree/bindings/display/panel/panel-simple.yaml

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@@ -280,6 +280,8 @@ properties: 
      - samsung,atna33xc20

        # Samsung 12.2" (2560x1600 pixels) TFT LCD panel

      - samsung,lsn122dl01-c01

        # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel

      - samsung,ltl101al01

        # Samsung Electronics 10.1" WSVGA TFT LCD panel

      - samsung,ltn101nt05

        # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel