Commit 6f32001f authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
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ARM: dts: imx6sx-nitrogen6sx: Use new pin names with DCE/DTE for UART pins 



Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this
is to distinguish the DCE/DTE functions.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 02ce1ddc

arch/arm/boot/dts/imx6sx-nitrogen6sx.dts

+10 −10
Original line number Diff line number Diff line
@@ -484,31 +484,31 @@ 


	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1

			MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1

			MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX		0x1b0b1

			MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX		0x1b0b1

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX6SX_PAD_GPIO1_IO06__UART2_TX		0x1b0b1

			MX6SX_PAD_GPIO1_IO07__UART2_RX		0x1b0b1

			MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX		0x1b0b1

			MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX		0x1b0b1

		>;

	};



	pinctrl_uart3: uart3grp {

		fsl,pins = <

			MX6SX_PAD_QSPI1B_SS0_B__UART3_TX	0x1b0b1

			MX6SX_PAD_QSPI1B_SCLK__UART3_RX		0x1b0b1

			MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX		0x1b0b1

			MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX		0x1b0b1

		>;

	};



	pinctrl_uart5: uart5grp {

		fsl,pins = <

			MX6SX_PAD_KEY_COL3__UART5_TX		0x1b0b1

			MX6SX_PAD_KEY_ROW3__UART5_RX		0x1b0b1

			MX6SX_PAD_SD3_DATA6__UART3_RTS_B	0x1b0b1

			MX6SX_PAD_SD3_DATA7__UART3_CTS_B	0x1b0b1

			MX6SX_PAD_KEY_COL3__UART5_DCE_TX		0x1b0b1

			MX6SX_PAD_KEY_ROW3__UART5_DCE_RX		0x1b0b1

			MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS		0x1b0b1

			MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS		0x1b0b1

		>;

	};