Commit 6f259bf1 authored by kartik's avatar kartik Committed by Thierry Reding
Browse files

soc/tegra: fuse: Update nvmem cell list 



Update tegra_fuse_cells with below entries:

 - gcplex-config-fuse:
     Configuration bits for GPU, used to enable/disable write protected
     region used for storing GPU firmware.
 - pdi0:
     Unique per chip public identifier.
 - pdi1:
     Unique per chip public identifier.

Signed-off-by: default avatarPrathamesh Shete <pshete@nvidia.com>
Signed-off-by: default avatarKartik <kkartik@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 1e5cf145

drivers/soc/tegra/fuse/fuse-tegra.c

+19 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2013-2021, NVIDIA CORPORATION.  All rights reserved.

 */



#include <linux/clk.h>
@@ -161,6 +161,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { 
		.bytes = 4,

		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "gcplex-config-fuse",

		.offset = 0x1c8,

		.bytes = 4,

		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "tsensor-realignment",

		.offset = 0x1fc,
@@ -179,6 +185,18 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { 
		.bytes = 4,

		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "pdi0",

		.offset = 0x300,

		.bytes = 4,

		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "pdi1",

		.offset = 0x304,

		.bytes = 4,

		.bit_offset = 0,

		.nbits = 32,

	},

};