Commit 6f0f70cd authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Mark per-engine-reset as supported on gen7 



The benefit of only resetting a single engine is that we leave other
streams of userspace work intact across a hang; vital for process
isolation. We had wired up individual engine resets for gen6, but only
enabled it from gen8; now let's turn it on for the forgotten gen7. gen6
is still a mystery as how to unravel some global state that appears to
be reset along with an engine (in particular the ppgtt enabling in
GFX_MODE).

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210119110802.22228-6-chris@chris-wilson.co.uk
parent 8fd7b58a

drivers/gpu/drm/i915/i915_pci.c

+3 −2
Original line number Diff line number Diff line
@@ -455,6 +455,7 @@ static const struct intel_device_info snb_m_gt2_info = { 
	.has_llc = 1, \

	.has_rc6 = 1, \

	.has_rc6p = 1, \

	.has_reset_engine = true, \

	.has_rps = true, \

	.dma_mask_size = 40, \

	.ppgtt_type = INTEL_PPGTT_ALIASING, \
@@ -513,6 +514,7 @@ static const struct intel_device_info vlv_info = { 
	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),

	.has_runtime_pm = 1,

	.has_rc6 = 1,

	.has_reset_engine = true,

	.has_rps = true,

	.display.has_gmch = 1,

	.display.has_hotplug = 1,
@@ -571,8 +573,7 @@ static const struct intel_device_info hsw_gt3_info = { 
	.dma_mask_size = 39, \

	.ppgtt_type = INTEL_PPGTT_FULL, \

	.ppgtt_size = 48, \

	.has_64bit_reloc = 1, \

	.has_reset_engine = 1

	.has_64bit_reloc = 1



#define BDW_PLATFORM \

	GEN8_FEATURES, \