Commit 6edd302a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-next' 



Guangbin Huang says:

====================
net: hns3: updates for -next

This series includes some updates for the HNS3 ethernet driver.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 39a7d726 08aa17a0

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+6 −4
Original line number Diff line number Diff line
@@ -99,11 +99,11 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_CQ_B,

};



#define hnae3_dev_fd_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)

#define hnae3_ae_dev_fd_supported(ae_dev) \

		test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)



#define hnae3_dev_gro_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps)

#define hnae3_ae_dev_gro_supported(ae_dev) \

		test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)



#define hnae3_dev_fec_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
@@ -223,6 +223,8 @@ enum hnae3_fec_mode { 
	HNAE3_FEC_AUTO = 0,

	HNAE3_FEC_BASER,

	HNAE3_FEC_RS,

	HNAE3_FEC_LLRS,

	HNAE3_FEC_NONE,

	HNAE3_FEC_USER_DEF,

};

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+9 −3
Original line number Diff line number Diff line
@@ -52,9 +52,9 @@ void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read) 
static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev,

					      bool is_pf)

{

	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);

	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);

	if (is_pf && ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {

	if (is_pf) {

		set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);

		set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);

		set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);

	}
@@ -91,6 +91,7 @@ int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, 
			hnae3_set_bit(compat, HCLGE_COMM_PHY_IMP_EN_B, 1);

		hnae3_set_bit(compat, HCLGE_COMM_MAC_STATS_EXT_EN_B, 1);

		hnae3_set_bit(compat, HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B, 1);

		hnae3_set_bit(compat, HCLGE_COMM_LLRS_FEC_EN_B, 1);



		req->compat = cpu_to_le32(compat);

	}
@@ -150,6 +151,8 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},

	{HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},

	{HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},

	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},

	{HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
@@ -162,6 +165,7 @@ static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},

	{HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},

	{HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},

	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},

};



static void
@@ -220,8 +224,10 @@ int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev, 
					 HNAE3_PCI_REVISION_BIT_SIZE;

	ae_dev->dev_version |= ae_dev->pdev->revision;



	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)

	if (ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {

		hclge_comm_set_default_capability(ae_dev, is_pf);

		return 0;

	}



	hclge_comm_parse_capability(ae_dev, is_pf, resp);

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+3 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#define HCLGE_COMM_PHY_IMP_EN_B			2

#define HCLGE_COMM_MAC_STATS_EXT_EN_B		3

#define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B	4

#define HCLGE_COMM_LLRS_FEC_EN_B		5



#define hclge_comm_dev_phy_imp_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
@@ -339,6 +340,8 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,

	HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,

	HCLGE_COMM_CAP_CQ_B = 18,

	HCLGE_COMM_CAP_GRO_B = 20,

	HCLGE_COMM_CAP_FD_B = 21,

};



enum HCLGE_COMM_API_CAP_BITS {

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+3 −4
Original line number Diff line number Diff line
@@ -3271,12 +3271,11 @@ static void hns3_set_default_feature(struct net_device *netdev) 
		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |

		NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;



	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {

	if (hnae3_ae_dev_gro_supported(ae_dev))

		netdev->features |= NETIF_F_GRO_HW;



		if (!(h->flags & HNAE3_SUPPORT_VF))

	if (hnae3_ae_dev_fd_supported(ae_dev))

		netdev->features |= NETIF_F_NTUPLE;

	}



	if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))

		netdev->features |= NETIF_F_GSO_UDP_L4;

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

+9 −6
Original line number Diff line number Diff line
@@ -1621,12 +1621,12 @@ static unsigned int loc_to_eth_fec(u8 loc_fec) 
		eth_fec |= ETHTOOL_FEC_AUTO;

	if (loc_fec & BIT(HNAE3_FEC_RS))

		eth_fec |= ETHTOOL_FEC_RS;

	if (loc_fec & BIT(HNAE3_FEC_LLRS))

		eth_fec |= ETHTOOL_FEC_LLRS;

	if (loc_fec & BIT(HNAE3_FEC_BASER))

		eth_fec |= ETHTOOL_FEC_BASER;



	/* if nothing is set, then FEC is off */

	if (!eth_fec)

		eth_fec = ETHTOOL_FEC_OFF;

	if (loc_fec & BIT(HNAE3_FEC_NONE))

		eth_fec |= ETHTOOL_FEC_OFF;



	return eth_fec;

}
@@ -1637,12 +1637,13 @@ static unsigned int eth_to_loc_fec(unsigned int eth_fec) 
	u32 loc_fec = 0;



	if (eth_fec & ETHTOOL_FEC_OFF)

		return loc_fec;



		loc_fec |= BIT(HNAE3_FEC_NONE);

	if (eth_fec & ETHTOOL_FEC_AUTO)

		loc_fec |= BIT(HNAE3_FEC_AUTO);

	if (eth_fec & ETHTOOL_FEC_RS)

		loc_fec |= BIT(HNAE3_FEC_RS);

	if (eth_fec & ETHTOOL_FEC_LLRS)

		loc_fec |= BIT(HNAE3_FEC_LLRS);

	if (eth_fec & ETHTOOL_FEC_BASER)

		loc_fec |= BIT(HNAE3_FEC_BASER);
@@ -1668,6 +1669,8 @@ static int hns3_get_fecparam(struct net_device *netdev, 


	fec->fec = loc_to_eth_fec(fec_ability);

	fec->active_fec = loc_to_eth_fec(fec_mode);

	if (!fec->active_fec)

		fec->active_fec = ETHTOOL_FEC_OFF;



	return 0;

}