Commit 6e7c968e authored by Yihang Li's avatar Yihang Li Committed by ZhouJuan
Browse files

scsi: hisi_sas: Configure the initialization registers according to HBA model 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I6ZGK8


CVE: NA

----------------------------------------------------------------------

We use init_reg_v3_hw() to set some registers, for the latest HBA devices,
some of these HW registers are set through firmware. Therefore, different
HBA models are distinguished through pci_dev->revision.

Signed-off-by: default avatarYihang Li <liyihang9@huawei.com>
Reviewed-by: default avatarXiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: default avatarxiabing <xiabing12@h-partners.com>
parent 166c61a9

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

+12 −5
Original line number Diff line number Diff line
@@ -617,12 +617,12 @@ static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba) 


static void init_reg_v3_hw(struct hisi_hba *hisi_hba)

{

	struct pci_dev *pdev = hisi_hba->pci_dev;

	int i, j;



	/* Global registers init */

	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,

			 (u32)((1ULL << hisi_hba->queue_count) - 1));

	hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);

	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);

	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);

	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
@@ -642,6 +642,9 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 
	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);

	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);



	if (pdev->revision < 0x30)

		hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);



	interrupt_enable_v3_hw(hisi_hba);

	for (i = 0; i < hisi_hba->n_phy; i++) {

		enum sas_linkrate max;
@@ -659,7 +662,6 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 
		prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);

		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,

			prog_phy_link_rate);

		hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);

		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);

		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);

		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
@@ -670,12 +672,17 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);

		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);

		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);

		hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);

		hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,

				     0x30f4240);

		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);



		/* set value through firmware for the latest HBA */

		if (pdev->revision < 0x30) {

			hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);

			hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);

			/* used for 12G negotiate */

			hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);

		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);

		}



		/* get default FFE configuration for BIST */

		for (j = 0; j < FFE_CFG_MAX; j++) {