Commit 6e332df7 authored by Saheed O. Bolarinwa's avatar Saheed O. Bolarinwa Committed by Bjorn Helgaas
Browse files

PCI/ASPM: Stop caching device L0s, L1 acceptable exit latencies 

Previously we calculated the device's acceptable L0s and L1 exit latencies
in pcie_aspm_cap_init() and cached them in struct pcie_link_state.

These values are only used in pcie_aspm_check_latency() where they are
compared with the actual exit latencies of the link.  This path is used
when removing or changing the D state of the device, so it's relatively low
frequency.

To reduce the amount of per-link data we store, remove the acceptable[]
arrays from struct pcie_link_state and calculate them directly from the
already-cached Device Capabilities register when needed.

[bhelgaas: use endpoint->devcap instead of reading it again]
Link: https://lore.kernel.org/r/20211119193732.12343-4-refactormyself@gmail.com


Signed-off-by: default avatarSaheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 222578da

drivers/pci/pcie/aspm.c

+10 −19
Original line number Diff line number Diff line
@@ -65,12 +65,6 @@ struct pcie_link_state { 
	u32 clkpm_enabled:1;		/* Current Clock PM state */

	u32 clkpm_default:1;		/* Default Clock PM state by BIOS */

	u32 clkpm_disable:1;		/* Clock PM disabled */



	/*

	 * Endpoint acceptable latencies. A pcie downstream port only

	 * has one slot under it, so at most there are 8 functions.

	 */

	struct aspm_latency acceptable[8];

};



static int aspm_disabled, aspm_force;
@@ -389,7 +383,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) 


static void pcie_aspm_check_latency(struct pci_dev *endpoint)

{

	u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0;

	u32 latency, encoding, lnkcap_up, lnkcap_dw;

	u32 l1_switch_latency = 0;

	struct aspm_latency latency_up, latency_dw;

	struct aspm_latency *acceptable;

	struct pcie_link_state *link;
@@ -400,7 +395,14 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) 
		return;



	link = endpoint->bus->self->link_state;

	acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];



	/* Calculate endpoint L0s acceptable latency */

	encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;

	acceptable->l0s = calc_l0s_acceptable(encoding);



	/* Calculate endpoint L1 acceptable latency */

	encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;

	acceptable->l1 = calc_l1_acceptable(encoding);



	while (link) {

		struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
@@ -666,22 +668,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 


	/* Get and check endpoint acceptable latencies */

	list_for_each_entry(child, &linkbus->devices, bus_list) {

		u32 reg32, encoding;

		struct aspm_latency *acceptable =

			&link->acceptable[PCI_FUNC(child->devfn)];



		if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&

		    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)

			continue;



		pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);

		/* Calculate endpoint L0s acceptable latency */

		encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;

		acceptable->l0s = calc_l0s_acceptable(encoding);

		/* Calculate endpoint L1 acceptable latency */

		encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;

		acceptable->l1 = calc_l1_acceptable(encoding);



		pcie_aspm_check_latency(child);

	}

}