Commit 6e2bdf7d authored by Conor Dooley's avatar Conor Dooley Committed by Jassi Brar
Browse files

dt-bindings: mailbox: fix the mpfs' reg property 



The "data" region of the PolarFire SoC's system controller mailbox is
not one continuous register space - the system controller's QSPI sits
between the control and data registers. Split the "data" reg into two
parts: "data" & "control".

Fixes: 21355623 ("dt-bindings: soc/microchip: update syscontroller compatibles")
Fixes: ed9543d6 ("dt-bindings: add bindings for polarfire soc mailbox")
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
parent 7e5cd064

Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml

+11 −4
Original line number Diff line number Diff line
@@ -14,9 +14,15 @@ properties: 
    const: microchip,mpfs-mailbox



  reg:

    items:

      - description: mailbox data registers

    oneOf:

      - items:

          - description: mailbox control & data registers

          - description: mailbox interrupt registers

        deprecated: true

      - items:

          - description: mailbox control registers

          - description: mailbox interrupt registers

          - description: mailbox data registers



  interrupts:

    maxItems: 1
@@ -39,7 +45,8 @@ examples: 
      #size-cells = <2>;

      mbox: mailbox@37020000 {

        compatible = "microchip,mpfs-mailbox";

        reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;

        reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,

              <0x0 0x37020800 0x0 0x100>;

        interrupt-parent = <&L1>;

        interrupts = <96>;

        #mbox-cells = <1>;