Commit 6e28f56c authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'adin1100-industrial-PHY-support' 



Alexandru Tachici says:

====================
net: phy: adin1100: Add initial support for ADIN1100 industrial PHY

The ADIN1100 is a low power single port 10BASE-T1L transceiver designed for
industrial Ethernet applications and is compliant with the IEEE 802.3cg
Ethernet standard for long reach 10 Mb/s Single Pair Ethernet.

The ADIN1100 uses Auto-Negotiation capability in accordance
with IEEE 802.3 Clause 98, providing a mechanism for
exchanging information between PHYs to allow link partners to
agree to a common mode of operation.

The concluded operating mode is the transmit amplitude mode and
master/slave preference common across the two devices.

Both device and LP advertise their ability and request for
increased transmit at:
- BASE-T1 autonegotiation advertisement register [47:32]\
Clause 45.2.7.21 of Standard 802.3
- BIT(13) - 10BASE-T1L High Level Transmit Operating Mode Ability
- BIT(12) - 10BASE-T1L High Level Transmit Operating Mode Request

For 2.4 Vpp (high level transmit) operation, both devices need
to have the High Level Transmit Operating Mode Ability bit set,
and only one of them needs to have the High Level Transmit
Operating Mode Request bit set. Otherwise 1.0 Vpp transmit level
will be used.

Settings for eth1:
	Supported ports: [ TP	 MII ]
	Supported link modes:   10baseT1L/Full
	Supported pause frame use: Symmetric Receive-only
	Supports auto-negotiation: Yes
	Supported FEC modes: Not reported
	Advertised link modes:  10baseT1L/Full
	Advertised pause frame use: No
	Advertised auto-negotiation: Yes
	Advertised FEC modes: Not reported
	Link partner advertised link modes:  10baseT1L/Full
	Link partner advertised pause frame use: No
	Link partner advertised auto-negotiation: Yes
	Link partner advertised FEC modes: Not reported
	Speed: 10Mb/s
	Duplex: Full
	Auto-negotiation: on
	master-slave cfg: preferred slave
	master-slave status: slave
	Port: Twisted Pair
	PHYAD: 0
	Transceiver: external
	MDI-X: Unknown
	Link detected: yes
	SQI: 7/7

1. Add basic support for ADIN1100.

Alexandru Ardelean (1):
  net: phy: adin1100: Add initial support for ADIN1100 industrial PHY

1. Added 10baset-T1L link modes.

2. Added 10-BasetT1L registers.

3. Added Base-T1 auto-negotiation registers. For Base-T1 these
registers decide master/slave status and TX voltage of the
device and link partner.

4. Added 10BASE-T1L support in phy-c45.c. Now genphy functions will call
Base-T1 functions where registers don't match, like the auto-negotiation ones.

5. Convert MSE to SQI using a predefined table and allow user access
through ethtool.

6. DT bindings for the 2.4 Vpp transmit mode.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 411a1476 49714461

Documentation/devicetree/bindings/net/ethernet-phy.yaml

+9 −0
Original line number Diff line number Diff line
@@ -77,6 +77,15 @@ properties: 
    description:

      Maximum PHY supported speed in Mbits / seconds.



  phy-10base-t1l-2.4vpp:

    description: |

      tristate, request/disable 2.4 Vpp operating mode. The values are:

      0: Disable 2.4 Vpp operating mode.

      1: Request 2.4 Vpp operating mode from link partner.

      Absence of this property will leave configuration to default values.

    $ref: "/schemas/types.yaml#/definitions/uint32"

    enum: [0, 1]



  broken-turn-around:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

drivers/net/phy/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -83,6 +83,13 @@ config ADIN_PHY 
	  - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit

	    Ethernet PHY



config ADIN1100_PHY

	tristate "Analog Devices Industrial Ethernet T1L PHYs"

	help

	  Adds support for the Analog Devices Industrial T1L Ethernet PHYs.

	  Currently supports the:

	  - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY



config AQUANTIA_PHY

	tristate "Aquantia PHYs"

	help

drivers/net/phy/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ sfp-obj-$(CONFIG_SFP) += sfp-bus.o 
obj-y				+= $(sfp-obj-y) $(sfp-obj-m)



obj-$(CONFIG_ADIN_PHY)		+= adin.o

obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o

obj-$(CONFIG_AMD_PHY)		+= amd.o

aquantia-objs			+= aquantia_main.o

ifdef CONFIG_HWMON

drivers/net/phy/adin1100.c

0 → 100644
+292 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 *  Driver for Analog Devices Industrial Ethernet T1L PHYs

 *

 * Copyright 2020 Analog Devices Inc.

 */

#include <linux/kernel.h>

#include <linux/bitfield.h>

#include <linux/delay.h>

#include <linux/errno.h>

#include <linux/init.h>

#include <linux/module.h>

#include <linux/mii.h>

#include <linux/phy.h>

#include <linux/property.h>



#define PHY_ID_ADIN1100				0x0283bc81



#define ADIN_FORCED_MODE			0x8000

#define   ADIN_FORCED_MODE_EN			BIT(0)



#define ADIN_CRSM_SFT_RST			0x8810

#define   ADIN_CRSM_SFT_RST_EN			BIT(0)



#define ADIN_CRSM_SFT_PD_CNTRL			0x8812

#define   ADIN_CRSM_SFT_PD_CNTRL_EN		BIT(0)



#define ADIN_AN_PHY_INST_STATUS			0x8030

#define   ADIN_IS_CFG_SLV			BIT(2)

#define   ADIN_IS_CFG_MST			BIT(3)



#define ADIN_CRSM_STAT				0x8818

#define   ADIN_CRSM_SFT_PD_RDY			BIT(1)

#define   ADIN_CRSM_SYS_RDY			BIT(0)



#define ADIN_MSE_VAL				0x830B



#define ADIN_SQI_MAX	7



struct adin_mse_sqi_range {

	u16 start;

	u16 end;

};



static const struct adin_mse_sqi_range adin_mse_sqi_map[] = {

	{ 0x0A74, 0xFFFF },

	{ 0x084E, 0x0A74 },

	{ 0x0698, 0x084E },

	{ 0x053D, 0x0698 },

	{ 0x0429, 0x053D },

	{ 0x034E, 0x0429 },

	{ 0x02A0, 0x034E },

	{ 0x0000, 0x02A0 },

};



/**

 * struct adin_priv - ADIN PHY driver private data

 * @tx_level_2v4_able:		set if the PHY supports 2.4V TX levels (10BASE-T1L)

 * @tx_level_2v4:		set if the PHY requests 2.4V TX levels (10BASE-T1L)

 * @tx_level_prop_present:	set if the TX level is specified in DT

 */

struct adin_priv {

	unsigned int		tx_level_2v4_able:1;

	unsigned int		tx_level_2v4:1;

	unsigned int		tx_level_prop_present:1;

};



static int adin_read_status(struct phy_device *phydev)

{

	int ret;



	ret = genphy_c45_read_status(phydev);

	if (ret)

		return ret;



	ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);

	if (ret < 0)

		return ret;



	if (ret & ADIN_IS_CFG_SLV)

		phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;



	if (ret & ADIN_IS_CFG_MST)

		phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;



	return 0;

}



static int adin_config_aneg(struct phy_device *phydev)

{

	struct adin_priv *priv = phydev->priv;

	int ret;



	if (phydev->autoneg == AUTONEG_DISABLE) {

		ret = genphy_c45_pma_setup_forced(phydev);

		if (ret < 0)

			return ret;



		if (priv->tx_level_prop_present && priv->tx_level_2v4)

			ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,

					       MDIO_PMA_10T1L_CTRL_2V4_EN);

		else

			ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,

						 MDIO_PMA_10T1L_CTRL_2V4_EN);

		if (ret < 0)

			return ret;



		/* Force PHY to use above configurations */

		return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);

	}



	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);

	if (ret < 0)

		return ret;



	/* Request increased transmit level from LP. */

	if (priv->tx_level_prop_present && priv->tx_level_2v4) {

		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,

				       MDIO_AN_T1_ADV_H_10L_TX_HI |

				       MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);

		if (ret < 0)

			return ret;

	}



	/* Disable 2.4 Vpp transmit level. */

	if ((priv->tx_level_prop_present && !priv->tx_level_2v4) || !priv->tx_level_2v4_able) {

		ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,

					 MDIO_AN_T1_ADV_H_10L_TX_HI |

					 MDIO_AN_T1_ADV_H_10L_TX_HI_REQ);

		if (ret < 0)

			return ret;

	}



	return genphy_c45_config_aneg(phydev);

}



static int adin_set_powerdown_mode(struct phy_device *phydev, bool en)

{

	int ret;

	int val;



	val = en ? ADIN_CRSM_SFT_PD_CNTRL_EN : 0;

	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,

			    ADIN_CRSM_SFT_PD_CNTRL, val);

	if (ret < 0)

		return ret;



	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,

					 (ret & ADIN_CRSM_SFT_PD_RDY) == val,

					 1000, 30000, true);

}



static int adin_suspend(struct phy_device *phydev)

{

	return adin_set_powerdown_mode(phydev, true);

}



static int adin_resume(struct phy_device *phydev)

{

	return adin_set_powerdown_mode(phydev, false);

}



static int adin_set_loopback(struct phy_device *phydev, bool enable)

{

	if (enable)

		return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,

					BMCR_LOOPBACK);



	/* PCS loopback (according to 10BASE-T1L spec) */

	return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,

				 BMCR_LOOPBACK);

}



static int adin_soft_reset(struct phy_device *phydev)

{

	int ret;



	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);

	if (ret < 0)

		return ret;



	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,

					 (ret & ADIN_CRSM_SYS_RDY),

					 10000, 30000, true);

}



static int adin_get_features(struct phy_device *phydev)

{

	struct adin_priv *priv = phydev->priv;

	struct device *dev = &phydev->mdio.dev;

	int ret;

	u8 val;



	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);

	if (ret < 0)

		return ret;



	/* This depends on the voltage level from the power source */

	priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);



	phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n",

		   priv->tx_level_2v4_able ? "yes" : "no");



	priv->tx_level_prop_present = device_property_present(dev, "phy-10base-t1l-2.4vpp");

	if (priv->tx_level_prop_present) {

		ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);

		if (ret < 0)

			return ret;



		priv->tx_level_2v4 = val;

		if (!priv->tx_level_2v4 && priv->tx_level_2v4_able)

			phydev_info(phydev,

				    "PHY supports 2.4V TX level, but disabled via config\n");

	}



	linkmode_set_bit_array(phy_basic_ports_array, ARRAY_SIZE(phy_basic_ports_array),

			       phydev->supported);



	return genphy_c45_pma_read_abilities(phydev);

}



static int adin_get_sqi(struct phy_device *phydev)

{

	u16 mse_val;

	int sqi;

	int ret;



	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);

	if (ret < 0)

		return ret;

	else if (!(ret & MDIO_STAT1_LSTATUS))

		return 0;



	ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);

	if (ret < 0)

		return ret;



	mse_val = 0xFFFF & ret;

	for (sqi = 0; sqi < ARRAY_SIZE(adin_mse_sqi_map); sqi++) {

		if (mse_val >= adin_mse_sqi_map[sqi].start && mse_val <= adin_mse_sqi_map[sqi].end)

			return sqi;

	}



	return -EINVAL;

}



static int adin_get_sqi_max(struct phy_device *phydev)

{

	return ADIN_SQI_MAX;

}



static int adin_probe(struct phy_device *phydev)

{

	struct device *dev = &phydev->mdio.dev;

	struct adin_priv *priv;



	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);

	if (!priv)

		return -ENOMEM;



	phydev->priv = priv;



	return 0;

}



static struct phy_driver adin_driver[] = {

	{

		PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100),

		.name			= "ADIN1100",

		.get_features		= adin_get_features,

		.soft_reset		= adin_soft_reset,

		.probe			= adin_probe,

		.config_aneg		= adin_config_aneg,

		.read_status		= adin_read_status,

		.set_loopback		= adin_set_loopback,

		.suspend		= adin_suspend,

		.resume			= adin_resume,

		.get_sqi		= adin_get_sqi,

		.get_sqi_max		= adin_get_sqi_max,

	},

};



module_phy_driver(adin_driver);



static struct mdio_device_id __maybe_unused adin_tbl[] = {

	{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },

	{ }

};



MODULE_DEVICE_TABLE(mdio, adin_tbl);

MODULE_DESCRIPTION("Analog Devices Industrial Ethernet T1L PHY driver");

MODULE_LICENSE("Dual BSD/GPL");

drivers/net/phy/phy-c45.c

+252 −5
Original line number Diff line number Diff line
@@ -8,6 +8,25 @@ 
#include <linux/mii.h>

#include <linux/phy.h>



/**

 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities

 * @phydev: target phy_device struct

 */

static bool genphy_c45_baset1_able(struct phy_device *phydev)

{

	int val;



	if (phydev->pma_extable == -ENODATA) {

		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);

		if (val < 0)

			return false;



		phydev->pma_extable = val;

	}



	return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);

}



/**

 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support

 * @phydev: target phy_device struct
@@ -80,6 +99,9 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev) 


	switch (phydev->speed) {

	case SPEED_10:

		if (genphy_c45_baset1_able(phydev))

			ctrl2 |= MDIO_PMA_CTRL2_BASET1;

		else

			ctrl2 |= MDIO_PMA_CTRL2_10BT;

		break;

	case SPEED_100:
@@ -118,10 +140,95 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev) 
	if (ret < 0)

		return ret;



	if (genphy_c45_baset1_able(phydev)) {

		int ctl = 0;



		switch (phydev->master_slave_set) {

		case MASTER_SLAVE_CFG_MASTER_PREFERRED:

		case MASTER_SLAVE_CFG_MASTER_FORCE:

			ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;

			break;

		case MASTER_SLAVE_CFG_SLAVE_FORCE:

		case MASTER_SLAVE_CFG_SLAVE_PREFERRED:

		case MASTER_SLAVE_CFG_UNKNOWN:

		case MASTER_SLAVE_CFG_UNSUPPORTED:

			break;

		default:

			phydev_warn(phydev, "Unsupported Master/Slave mode\n");

			return -EOPNOTSUPP;

		}



		ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,

				     MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);

		if (ret < 0)

			return ret;

	}



	return genphy_c45_an_disable_aneg(phydev);

}

EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);



/* Sets master/slave preference and supported technologies.

 * The preference is set in the BIT(4) of BASE-T1 AN

 * advertisement register 7.515 and whether the status

 * is forced or not, it is set in the BIT(12) of BASE-T1

 * AN advertisement register 7.514.

 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation

 * advertisement register [31:16] if supported.

 */

static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)

{

	int changed = 0;

	u16 adv_l = 0;

	u16 adv_m = 0;

	int ret;



	switch (phydev->master_slave_set) {

	case MASTER_SLAVE_CFG_MASTER_FORCE:

	case MASTER_SLAVE_CFG_SLAVE_FORCE:

		adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;

		break;

	case MASTER_SLAVE_CFG_MASTER_PREFERRED:

	case MASTER_SLAVE_CFG_SLAVE_PREFERRED:

		break;

	default:

		break;

	}



	switch (phydev->master_slave_set) {

	case MASTER_SLAVE_CFG_MASTER_FORCE:

	case MASTER_SLAVE_CFG_MASTER_PREFERRED:

		adv_m |= MDIO_AN_T1_ADV_M_MST;

		break;

	case MASTER_SLAVE_CFG_SLAVE_FORCE:

	case MASTER_SLAVE_CFG_SLAVE_PREFERRED:

		break;

	default:

		break;

	}



	adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);



	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,

				     (MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP

				     | MDIO_AN_T1_ADV_L_PAUSE_ASYM), adv_l);

	if (ret < 0)

		return ret;

	if (ret > 0)

		changed = 1;



	adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);



	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,

				     MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L, adv_m);

	if (ret < 0)

		return ret;

	if (ret > 0)

		changed = 1;



	return changed;

}



/**

 * genphy_c45_an_config_aneg - configure advertisement registers

 * @phydev: target phy_device struct
@@ -141,6 +248,9 @@ int genphy_c45_an_config_aneg(struct phy_device *phydev) 


	changed = genphy_config_eee_advert(phydev);



	if (genphy_c45_baset1_able(phydev))

		return genphy_c45_baset1_an_config_aneg(phydev);



	adv = linkmode_adv_to_mii_adv_t(phydev->advertising);



	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
@@ -178,8 +288,12 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 
 */

int genphy_c45_an_disable_aneg(struct phy_device *phydev)

{

	u16 reg = MDIO_CTRL1;



	if (genphy_c45_baset1_able(phydev))

		reg = MDIO_AN_T1_CTRL;



	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,

	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,

				  MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);

}

EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
@@ -194,7 +308,12 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 
 */

int genphy_c45_restart_aneg(struct phy_device *phydev)

{

	return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,

	u16 reg = MDIO_CTRL1;



	if (genphy_c45_baset1_able(phydev))

		reg = MDIO_AN_T1_CTRL;



	return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,

				MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);

}

EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
@@ -210,11 +329,15 @@ EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 
 */

int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)

{

	u16 reg = MDIO_CTRL1;

	int ret;



	if (genphy_c45_baset1_able(phydev))

		reg = MDIO_AN_T1_CTRL;



	if (!restart) {

		/* Configure and restart aneg if it wasn't set before */

		ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);

		ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);

		if (ret < 0)

			return ret;
@@ -242,7 +365,13 @@ EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 
 */

int genphy_c45_aneg_done(struct phy_device *phydev)

{

	int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);

	int reg = MDIO_STAT1;

	int val;



	if (genphy_c45_baset1_able(phydev))

		reg = MDIO_AN_T1_STAT;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);



	return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;

}
@@ -307,6 +436,49 @@ int genphy_c45_read_link(struct phy_device *phydev) 
}

EXPORT_SYMBOL_GPL(genphy_c45_read_link);



/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check

 * if autoneg is complete. If so read the BASE-T1 Autonegotiation

 * Advertisement registers filling in the link partner advertisement,

 * pause and asym_pause members in phydev.

 */

static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)

{

	int val;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);

	if (val < 0)

		return val;



	if (!(val & MDIO_AN_STAT1_COMPLETE)) {

		linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);

		mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);

		mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);



		phydev->pause = 0;

		phydev->asym_pause = 0;



		return 0;

	}



	linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);

	if (val < 0)

		return val;



	mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);

	phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;

	phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);

	if (val < 0)

		return val;



	mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);



	return 0;

}



/**

 * genphy_c45_read_lpa - read the link partner advertisement and pause

 * @phydev: target phy_device struct
@@ -321,6 +493,9 @@ int genphy_c45_read_lpa(struct phy_device *phydev) 
{

	int val;



	if (genphy_c45_baset1_able(phydev))

		return genphy_c45_baset1_read_lpa(phydev);



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);

	if (val < 0)

		return val;
@@ -399,6 +574,17 @@ int genphy_c45_read_pma(struct phy_device *phydev) 


	phydev->duplex = DUPLEX_FULL;



	if (genphy_c45_baset1_able(phydev)) {

		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);

		if (val < 0)

			return val;



		if (MDIO_PMA_PMD_BT1_CTRL_CFG_MST)

			phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;

		else

			phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
@@ -530,12 +716,67 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev) 
					 phydev->supported,

					 val & MDIO_PMA_NG_EXTABLE_5GBT);

		}



		if (val & MDIO_PMA_EXTABLE_BT1) {

			val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);

			if (val < 0)

				return val;



			linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,

					 phydev->supported,

					 val & MDIO_PMA_PMD_BT1_B10L_ABLE);



			val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);

			if (val < 0)

				return val;



			linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,

					 phydev->supported,

					 val & MDIO_AN_STAT1_ABLE);

		}

	}



	return 0;

}

EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);



/* Read master/slave preference from registers.

 * The preference is read from the BIT(4) of BASE-T1 AN

 * advertisement register 7.515 and whether the preference

 * is forced or not, it is read from BASE-T1 AN advertisement

 * register 7.514.

 */

static int genphy_c45_baset1_read_status(struct phy_device *phydev)

{

	int ret;

	int cfg;



	phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;

	phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;



	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);

	if (ret < 0)

		return ret;



	cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);

	if (cfg < 0)

		return cfg;



	if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {

		if (cfg & MDIO_AN_T1_ADV_M_MST)

			phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;

		else

			phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;

	} else {

		if (cfg & MDIO_AN_T1_ADV_M_MST)

			phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;

		else

			phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;

	}



	return 0;

}



/**

 * genphy_c45_read_status - read PHY status

 * @phydev: target phy_device struct
@@ -560,6 +801,12 @@ int genphy_c45_read_status(struct phy_device *phydev) 
		if (ret)

			return ret;



		if (genphy_c45_baset1_able(phydev)) {

			ret = genphy_c45_baset1_read_status(phydev);

			if (ret < 0)

				return ret;

		}



		phy_resolve_aneg_linkmode(phydev);

	} else {

		ret = genphy_c45_read_pma(phydev);