Commit 6de85909 authored by Zenghui Yu's avatar Zenghui Yu Committed by Zheng Zengkai
Browse files

KVM: arm64: Add support for probing Hisi ncsnp capability 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4IZOS


CVE: NA

----------------------------------------------------

Kunpeng 920 offers the HHA ncsnp capability, with which hypervisor doesn't
need to perform a lot of cache maintenance like before (in case the guest
has some non-cacheable Stage-1 mappings). Currently we apply this hardware
capability when

 - vCPU switching MMU+caches on/off
 - creating Stage-2 mappings for Daborts

Signed-off-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: default avatarYanan Wang <wangyanan55@huawei.com>
Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent bb6ee10a

arch/arm64/include/asm/hisi_cpu_model.h

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ enum hisi_cpu_type { 
};



extern enum hisi_cpu_type hi_cpu_type;

extern bool kvm_ncsnp_support;



void probe_hisi_cpu_type(void);

void probe_hisi_ncsnp_support(void);

#endif /* __HISI_CPU_MODEL_H__ */

arch/arm64/include/asm/kvm_mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) 
	 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to

	 * PoU is not required either in this case.

	 */

	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

	if (kvm_ncsnp_support || cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

		return;



	kvm_flush_dcache_to_poc(va, size);

arch/arm64/kvm/arm.c

+2 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ static bool vgic_present; 


/* Hisi cpu type enum */

enum hisi_cpu_type hi_cpu_type = UNKNOWN_HI_TYPE;

bool kvm_ncsnp_support;



static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled);

DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
@@ -1838,6 +1839,7 @@ int kvm_arch_init(void *opaque) 


	/* Probe the Hisi CPU type */

	probe_hisi_cpu_type();

	probe_hisi_ncsnp_support();



	in_hyp_mode = is_kernel_in_hyp_mode();

arch/arm64/kvm/hisi_cpu_model.c

+34 −0
Original line number Diff line number Diff line
@@ -81,3 +81,37 @@ void probe_hisi_cpu_type(void) 
	if (hi_cpu_type == UNKNOWN_HI_TYPE)

		pr_warn("UNKNOWN Hisi cpu type.\n");

}



#define NCSNP_MMIO_BASE	0x20107E238



/*

 * We have the fantastic HHA ncsnp capability on Kunpeng 920,

 * with which hypervisor doesn't need to perform a lot of cache

 * maintenance like before (in case the guest has non-cacheable

 * Stage-1 mappings).

 */

void probe_hisi_ncsnp_support(void)

{

	void __iomem *base;

	unsigned int high;



	kvm_ncsnp_support = false;



	if (hi_cpu_type != HI_1620)

		goto out;



	base = ioremap(NCSNP_MMIO_BASE, 4);

	if (!base) {

		pr_err("Unable to map MMIO region when probing ncsnp!\n");

		goto out;

	}



	high = readl_relaxed(base) >> 28;

	iounmap(base);

	if (high != 0x1)

		kvm_ncsnp_support = true;



out:

	kvm_info("Hisi ncsnp: %s\n", kvm_ncsnp_support ? "enabled" :

							 "disabled");

}

arch/arm64/kvm/hyp/pgtable.c

+2 −2
Original line number Diff line number Diff line
@@ -643,7 +643,7 @@ int kvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, 


static void stage2_flush_dcache(void *addr, u64 size)

{

	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

	if (kvm_ncsnp_support || cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

		return;



	__flush_dcache_area(addr, size);
@@ -847,7 +847,7 @@ int kvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size) 
		.flags	= KVM_PGTABLE_WALK_LEAF,

	};



	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

	if (kvm_ncsnp_support || cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))

		return 0;



	return kvm_pgtable_walk(pgt, addr, size, &walker);