Commit 6de1bd74 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch 'sm8450-sm8550-gpucc-binding' into clk-for-6.5 

Bring GPUCC DeviceTree bindings for SM8450 and SM8550 in through a topic
branch to allow sharing it with the DeviceTree source tree as well.
parents 8fd492e7 778af143

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Graphics Clock & Reset Controller on SM8450



maintainers:

  - Konrad Dybcio <konrad.dybcio@linaro.org>



description: |

  Qualcomm graphics clock control module provides the clocks, resets and power

  domains on Qualcomm SoCs.



  See also::

    include/dt-bindings/clock/qcom,sm8450-gpucc.h

    include/dt-bindings/clock/qcom,sm8550-gpucc.h

    include/dt-bindings/reset/qcom,sm8450-gpucc.h



properties:

  compatible:

    enum:

      - qcom,sm8450-gpucc

      - qcom,sm8550-gpucc



  clocks:

    items:

      - description: Board XO source

      - description: GPLL0 main branch source

      - description: GPLL0 div branch source



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8450.h>

    #include <dt-bindings/clock/qcom,rpmh.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@3d90000 {

            compatible = "qcom,sm8450-gpucc";

            reg = <0 0x03d90000 0 0xa000>;

            clocks = <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,

                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

            #clock-cells = <1>;

            #reset-cells = <1>;

            #power-domain-cells = <1>;

        };

    };

...

include/dt-bindings/clock/qcom,sm8450-gpucc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H



/* Clocks */

#define GPU_CC_AHB_CLK				0

#define GPU_CC_CRC_AHB_CLK			1

#define GPU_CC_CX_APB_CLK			2

#define GPU_CC_CX_FF_CLK			3

#define GPU_CC_CX_GMU_CLK			4

#define GPU_CC_CX_SNOC_DVM_CLK			5

#define GPU_CC_CXO_AON_CLK			6

#define GPU_CC_CXO_CLK				7

#define GPU_CC_DEMET_CLK			8

#define GPU_CC_DEMET_DIV_CLK_SRC		9

#define GPU_CC_FF_CLK_SRC			10

#define GPU_CC_FREQ_MEASURE_CLK			11

#define GPU_CC_GMU_CLK_SRC			12

#define GPU_CC_GX_FF_CLK			13

#define GPU_CC_GX_GFX3D_CLK			14

#define GPU_CC_GX_GFX3D_RDVM_CLK		15

#define GPU_CC_GX_GMU_CLK			16

#define GPU_CC_GX_VSENSE_CLK			17

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		18

#define GPU_CC_HUB_AHB_DIV_CLK_SRC		19

#define GPU_CC_HUB_AON_CLK			20

#define GPU_CC_HUB_CLK_SRC			21

#define GPU_CC_HUB_CX_INT_CLK			22

#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC		23

#define GPU_CC_MEMNOC_GFX_CLK			24

#define GPU_CC_MND1X_0_GFX3D_CLK		25

#define GPU_CC_MND1X_1_GFX3D_CLK		26

#define GPU_CC_PLL0				27

#define GPU_CC_PLL1				28

#define GPU_CC_SLEEP_CLK			29

#define GPU_CC_XO_CLK_SRC			30

#define GPU_CC_XO_DIV_CLK_SRC			31



/* GDSCs */

#define GPU_GX_GDSC				0

#define GPU_CX_GDSC				1



#endif

include/dt-bindings/clock/qcom,sm8550-gpucc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H



/* GPU_CC clocks */

#define GPU_CC_AHB_CLK						0

#define GPU_CC_CRC_AHB_CLK					1

#define GPU_CC_CX_FF_CLK					2

#define GPU_CC_CX_GMU_CLK					3

#define GPU_CC_CXO_AON_CLK					4

#define GPU_CC_CXO_CLK						5

#define GPU_CC_DEMET_CLK					6

#define GPU_CC_DEMET_DIV_CLK_SRC				7

#define GPU_CC_FF_CLK_SRC					8

#define GPU_CC_FREQ_MEASURE_CLK					9

#define GPU_CC_GMU_CLK_SRC					10

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				11

#define GPU_CC_HUB_AON_CLK					12

#define GPU_CC_HUB_CLK_SRC					13

#define GPU_CC_HUB_CX_INT_CLK					14

#define GPU_CC_MEMNOC_GFX_CLK					15

#define GPU_CC_MND1X_0_GFX3D_CLK				16

#define GPU_CC_MND1X_1_GFX3D_CLK				17

#define GPU_CC_PLL0						18

#define GPU_CC_PLL1						19

#define GPU_CC_SLEEP_CLK					20

#define GPU_CC_XO_CLK_SRC					21

#define GPU_CC_XO_DIV_CLK_SRC					22



/* GPU_CC power domains */

#define GPU_CC_CX_GDSC						0

#define GPU_CC_GX_GDSC						1



/* GPU_CC resets */

#define GPUCC_GPU_CC_ACD_BCR					0

#define GPUCC_GPU_CC_CX_BCR					1

#define GPUCC_GPU_CC_FAST_HUB_BCR				2

#define GPUCC_GPU_CC_FF_BCR					3

#define GPUCC_GPU_CC_GFX3D_AON_BCR				4

#define GPUCC_GPU_CC_GMU_BCR					5

#define GPUCC_GPU_CC_GX_BCR					6

#define GPUCC_GPU_CC_XO_BCR					7



#endif

include/dt-bindings/reset/qcom,sm8450-gpucc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2023, Linaro Limited

 */



#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H

#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H



#define GPUCC_GPU_CC_ACD_BCR			0

#define GPUCC_GPU_CC_CX_BCR			1

#define GPUCC_GPU_CC_FAST_HUB_BCR		2

#define GPUCC_GPU_CC_FF_BCR			3

#define GPUCC_GPU_CC_GFX3D_AON_BCR		4

#define GPUCC_GPU_CC_GMU_BCR			5

#define GPUCC_GPU_CC_GX_BCR			6

#define GPUCC_GPU_CC_XO_BCR			7

#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR		8



#endif