Commit 6ddbd37f authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementations 



Drop cross callings and multi-function APIs. Also avoid exposing
internal implementations details.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d698a2c4

drivers/gpu/drm/amd/include/kgd_pp_interface.h

+1 −1
Original line number Diff line number Diff line
@@ -404,7 +404,7 @@ struct amd_pm_funcs { 
	int (*get_dpm_clock_table)(void *handle,

				   struct dpm_clocks *clock_table);

	int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);

	int (*change_power_state)(void *handle);

	void (*pm_compute_clocks)(void *handle);

};



struct metrics_table_header {

drivers/gpu/drm/amd/pm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ AMD_PM = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/pm/,$(PM_LIBS))) 


include $(AMD_PM)



PM_MGR = amdgpu_dpm.o amdgpu_pm.o

PM_MGR = amdgpu_dpm.o amdgpu_pm.o amdgpu_dpm_internal.o



AMD_PM_POWER = $(addprefix $(AMD_PM_PATH)/,$(PM_MGR))

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

+22 −180
Original line number Diff line number Diff line
@@ -37,73 +37,6 @@ 
#define amdgpu_dpm_enable_bapm(adev, e) \

		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))



static void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)

{

	struct drm_device *ddev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct amdgpu_crtc *amdgpu_crtc;



	adev->pm.dpm.new_active_crtcs = 0;

	adev->pm.dpm.new_active_crtc_count = 0;

	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {

		list_for_each_entry(crtc,

				    &ddev->mode_config.crtc_list, head) {

			amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (amdgpu_crtc->enabled) {

				adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);

				adev->pm.dpm.new_active_crtc_count++;

			}

		}

	}

}



u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)

{

	struct drm_device *dev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct amdgpu_crtc *amdgpu_crtc;

	u32 vblank_in_pixels;

	u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */



	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

			amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {

				vblank_in_pixels =

					amdgpu_crtc->hw_mode.crtc_htotal *

					(amdgpu_crtc->hw_mode.crtc_vblank_end -

					amdgpu_crtc->hw_mode.crtc_vdisplay +

					(amdgpu_crtc->v_border * 2));



				vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;

				break;

			}

		}

	}



	return vblank_time_us;

}



static u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)

{

	struct drm_device *dev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct amdgpu_crtc *amdgpu_crtc;

	u32 vrefresh = 0;



	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

			amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {

				vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);

				break;

			}

		}

	}



	return vrefresh;

}



int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)

{

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
@@ -432,99 +365,23 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso 
	return ret;

}



void amdgpu_dpm_thermal_work_handler(struct work_struct *work)

{

	struct amdgpu_device *adev =

		container_of(work, struct amdgpu_device,

			     pm.dpm.thermal.work);

	/* switch to the thermal state */

	enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;

	int temp, size = sizeof(temp);



	if (!adev->pm.dpm_enabled)

		return;



	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,

				    (void *)&temp, &size)) {

		if (temp < adev->pm.dpm.thermal.min_temp)

			/* switch back the user state */

			dpm_state = adev->pm.dpm.user_state;

	} else {

		if (adev->pm.dpm.thermal.high_to_low)

			/* switch back the user state */

			dpm_state = adev->pm.dpm.user_state;

	}

	mutex_lock(&adev->pm.mutex);

	if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)

		adev->pm.dpm.thermal_active = true;

	else

		adev->pm.dpm.thermal_active = false;

	adev->pm.dpm.state = dpm_state;

	mutex_unlock(&adev->pm.mutex);



	amdgpu_dpm_compute_clocks(adev);

}



void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev)

{

	int i = 0;

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;



	if (!adev->pm.dpm_enabled)

		return;



	if (adev->mode_info.num_crtc)

		amdgpu_display_bandwidth_update(adev);

	if (!pp_funcs->pm_compute_clocks)

		return;



	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {

		struct amdgpu_ring *ring = adev->rings[i];

		if (ring && ring->sched.ready)

			amdgpu_fence_wait_empty(ring);

	}



	if ((adev->family == AMDGPU_FAMILY_SI) ||

	     (adev->family == AMDGPU_FAMILY_KV)) {

		mutex_lock(&adev->pm.mutex);

		amdgpu_dpm_get_active_displays(adev);

		adev->powerplay.pp_funcs->change_power_state(adev->powerplay.pp_handle);

		mutex_unlock(&adev->pm.mutex);

	} else {

		if (!amdgpu_device_has_dc_support(adev)) {

			mutex_lock(&adev->pm.mutex);

			amdgpu_dpm_get_active_displays(adev);

			adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;

			adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);

			adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);

			/* we have issues with mclk switching with

			 * refresh rates over 120 hz on the non-DC code.

			 */

			if (adev->pm.pm_display_cfg.vrefresh > 120)

				adev->pm.pm_display_cfg.min_vblank_time = 0;

			if (adev->powerplay.pp_funcs->display_configuration_change)

				adev->powerplay.pp_funcs->display_configuration_change(

							adev->powerplay.pp_handle,

							&adev->pm.pm_display_cfg);

			mutex_unlock(&adev->pm.mutex);

		}

		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);

	}

	pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);

}



void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)

{

	int ret = 0;



	if (adev->family == AMDGPU_FAMILY_SI) {

		mutex_lock(&adev->pm.mutex);

		if (enable) {

			adev->pm.dpm.uvd_active = true;

			adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;

		} else {

			adev->pm.dpm.uvd_active = false;

		}

		mutex_unlock(&adev->pm.mutex);



		amdgpu_dpm_compute_clocks(adev);

	} else {

	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);

	if (ret)

		DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
@@ -542,31 +399,16 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 
							       true);

	}

}

}



void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)

{

	int ret = 0;



	if (adev->family == AMDGPU_FAMILY_SI) {

		mutex_lock(&adev->pm.mutex);

		if (enable) {

			adev->pm.dpm.vce_active = true;

			/* XXX select vce level based on ring/task */

			adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;

		} else {

			adev->pm.dpm.vce_active = false;

		}

		mutex_unlock(&adev->pm.mutex);



		amdgpu_dpm_compute_clocks(adev);

	} else {

	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);

	if (ret)

		DRM_ERROR("Dpm %s vce failed, ret = %d. \n",

			  enable ? "enable" : "disable", ret);

}

}



void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)

{

drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c

0 → 100644
+94 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include "amdgpu.h"

#include "amdgpu_display.h"

#include "hwmgr.h"

#include "amdgpu_smu.h"



void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)

{

	struct drm_device *ddev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct amdgpu_crtc *amdgpu_crtc;



	adev->pm.dpm.new_active_crtcs = 0;

	adev->pm.dpm.new_active_crtc_count = 0;

	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {

		list_for_each_entry(crtc,

				    &ddev->mode_config.crtc_list, head) {

			amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (amdgpu_crtc->enabled) {

				adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);

				adev->pm.dpm.new_active_crtc_count++;

			}

		}

	}

}



u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)

{

	struct drm_device *dev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct amdgpu_crtc *amdgpu_crtc;

	u32 vblank_in_pixels;

	u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */



	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

			amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {

				vblank_in_pixels =

					amdgpu_crtc->hw_mode.crtc_htotal *

					(amdgpu_crtc->hw_mode.crtc_vblank_end -

					amdgpu_crtc->hw_mode.crtc_vdisplay +

					(amdgpu_crtc->v_border * 2));



				vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;

				break;

			}

		}

	}



	return vblank_time_us;

}



u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)

{

	struct drm_device *dev = adev_to_drm(adev);

	struct drm_crtc *crtc;

	struct amdgpu_crtc *amdgpu_crtc;

	u32 vrefresh = 0;



	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

			amdgpu_crtc = to_amdgpu_crtc(crtc);

			if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {

				vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);

				break;

			}

		}

	}



	return vrefresh;

}

drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h

+0 −2
Original line number Diff line number Diff line
@@ -428,8 +428,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 
int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,

			   void *data, uint32_t *size);



void amdgpu_dpm_thermal_work_handler(struct work_struct *work);



void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);

void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);

void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);