Commit 6db5e0c8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2022-07-06' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- Suspend fixes for Display (Jose)
- Properly block D3Cold for now (Anshuman)
- Eliminate PIPECONF RMWs from .color_commit()(Ville)
- Display info clean-up (Ville)
- Fix error code (Dan)
- Fix possible refcount leak on DP MST (Hangyu)
- Other general display clean-ups (Jani, Tom)
- Add bios debug logs (Jani)
- PCH type clean-up (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YsZNJUVh0iHOtORz@intel.com
parents 344feb7c 3d9c653c

drivers/gpu/drm/i915/display/intel_bios.c

+6 −2
Original line number Diff line number Diff line
@@ -2670,8 +2670,6 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata) 


	sanitize_device_type(devdata, port);



	print_ddi_port(devdata, port);



	if (intel_bios_encoder_supports_dvi(devdata))

		sanitize_ddc_pin(devdata, port);
@@ -2689,12 +2687,18 @@ static bool has_ddi_port_info(struct drm_i915_private *i915) 
static void parse_ddi_ports(struct drm_i915_private *i915)

{

	struct intel_bios_encoder_data *devdata;

	enum port port;



	if (!has_ddi_port_info(i915))

		return;



	list_for_each_entry(devdata, &i915->vbt.display_devices, node)

		parse_ddi_port(devdata);



	for_each_port(port) {

		if (i915->vbt.ports[port])

			print_ddi_port(i915->vbt.ports[port], port);

	}

}



static void

drivers/gpu/drm/i915/display/intel_color.c

+19 −30
Original line number Diff line number Diff line
@@ -505,30 +505,19 @@ static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state) 


static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	u32 val;



	val = intel_de_read(dev_priv, PIPECONF(pipe));

	val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;

	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);

	intel_de_write(dev_priv, PIPECONF(pipe), val);

	/* update PIPECONF GAMMA_MODE */

	i9xx_set_pipeconf(crtc_state);

}



static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	u32 val;



	val = intel_de_read(dev_priv, PIPECONF(pipe));

	val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;

	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);

	intel_de_write(dev_priv, PIPECONF(pipe), val);

	/* update PIPECONF GAMMA_MODE */

	ilk_set_pipeconf(crtc_state);



	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(pipe),

	intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),

			  crtc_state->csc_mode);

}
@@ -852,7 +841,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;

	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;



	/*
@@ -894,7 +883,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;



	/*

	 * When setting the auto-increment bit, the hardware seems to
@@ -1346,10 +1335,10 @@ static int check_luts(const struct intel_crtc_state *crtc_state) 
		return -EINVAL;

	}



	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;

	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;

	gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;

	degamma_length = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;

	gamma_length = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	degamma_tests = INTEL_INFO(dev_priv)->display.color.degamma_lut_tests;

	gamma_tests = INTEL_INFO(dev_priv)->display.color.gamma_lut_tests;



	if (check_lut_size(degamma_lut, degamma_length) ||

	    check_lut_size(gamma_lut, gamma_length))
@@ -1885,7 +1874,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -1928,7 +1917,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state) 
static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -1989,7 +1978,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 
static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -2040,7 +2029,7 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, hw_lut_size = ivb_lut_10_size(prec_index);

	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	int lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -2093,7 +2082,7 @@ static struct drm_property_blob * 
icl_read_lut_multi_segment(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;

	int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;

	enum pipe pipe = crtc->pipe;

	struct drm_property_blob *blob;

	struct drm_color_lut *lut;
@@ -2230,7 +2219,7 @@ static const struct intel_color_funcs ilk_color_funcs = { 
void intel_color_init(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;

	bool has_ctm = INTEL_INFO(dev_priv)->display.color.degamma_lut_size != 0;



	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
@@ -2261,7 +2250,7 @@ void intel_color_init(struct intel_crtc *crtc) 
	}



	drm_crtc_enable_color_mgmt(&crtc->base,

				   INTEL_INFO(dev_priv)->color.degamma_lut_size,

				   INTEL_INFO(dev_priv)->display.color.degamma_lut_size,

				   has_ctm,

				   INTEL_INFO(dev_priv)->color.gamma_lut_size);

				   INTEL_INFO(dev_priv)->display.color.gamma_lut_size);

}

drivers/gpu/drm/i915/display/intel_ddi.c

+1 −1
Original line number Diff line number Diff line
@@ -4179,7 +4179,7 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 
	if (port == PORT_D)

		return HPD_PORT_A;



	if (HAS_PCH_MCC(dev_priv))

	if (HAS_PCH_TGP(dev_priv))

		return icl_hpd_pin(dev_priv, port);



	return HPD_PORT_A + port - PORT_A;

drivers/gpu/drm/i915/display/intel_display.c

+22 −8
Original line number Diff line number Diff line
@@ -126,8 +126,6 @@ 


static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);

static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);

static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);

static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);

static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
@@ -3015,14 +3013,18 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, 
	intel_bigjoiner_adjust_pipe_src(pipe_config);

}



static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)

void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	u32 pipeconf = 0;



	/* we keep both pipes enabled on 830 */

	if (IS_I830(dev_priv))

	/*

	 * - We keep both pipes enabled on 830

	 * - During modeset the pipe is still disabled and must remain so

	 * - During fastset the pipe is already enabled and must remain so

	 */

	if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))

		pipeconf |= PIPECONF_ENABLE;



	if (crtc_state->double_wide)
@@ -3335,14 +3337,19 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
	return ret;

}



static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)

void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	u32 val;

	u32 val = 0;



	val = 0;

	/*

	 * - During modeset the pipe is still disabled and must remain so

	 * - During fastset the pipe is already enabled and must remain so

	 */

	if (!intel_crtc_needs_modeset(crtc_state))

		val |= PIPECONF_ENABLE;



	switch (crtc_state->pipe_bpp) {

	default:
@@ -3401,6 +3408,13 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	u32 val = 0;



	/*

	 * - During modeset the pipe is still disabled and must remain so

	 * - During fastset the pipe is already enabled and must remain so

	 */

	if (!intel_crtc_needs_modeset(crtc_state))

		val |= PIPECONF_ENABLE;



	if (IS_HASWELL(dev_priv) && crtc_state->dither)

		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;

drivers/gpu/drm/i915/display/intel_display.h

+3 −1
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ enum plane_id { 


#define for_each_dbuf_slice(__dev_priv, __slice) \

	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \

		for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))

		for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))



#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \

	for_each_dbuf_slice((__dev_priv), (__slice)) \
@@ -567,6 +567,8 @@ bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);



void intel_plane_destroy(struct drm_plane *plane);

void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);

void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);

void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);

void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);

void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);