Commit 6d9ba612 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by Michael Ellerman
Browse files

powerpc/powernv/pci: Drop unused MSI code 



MSIs should be fully managed by the PCI and IRQ subsystems now.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210701132750.1475580-26-clg@kaod.org
parent 3005123e

arch/powerpc/platforms/powernv/pci-ioda.c

+0 −27
Original line number Diff line number Diff line
@@ -2080,29 +2080,6 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, 
	return 0;

}



static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,

				  unsigned int hwirq, unsigned int virq,

				  unsigned int is_64, struct msi_msg *msg)

{

	struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);

	unsigned int xive_num = hwirq - phb->msi_base;

	int rc;



	rc = __pnv_pci_ioda_msi_setup(phb, dev, xive_num, is_64, msg);

	if (rc)

		return rc;



	/* P8 only */

	pnv_set_msi_irq_chip(phb, virq);



	pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"

		 " address=%x_%08x data=%x PE# %x\n",

		 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,

		 msg->address_hi, msg->address_lo, msg->data, pe->pe_number);



	return 0;

}



/*

 * The msi_free() op is called before irq_domain_free_irqs_top() when

 * the handler data is still available. Use that to clear the XIVE
@@ -2327,8 +2304,6 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) 
		return;

	}



	phb->msi_setup = pnv_pci_ioda_msi_setup;

	phb->msi32_support = 1;

	pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",

		count, phb->msi_base);
@@ -2936,8 +2911,6 @@ static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { 
	.dma_dev_setup		= pnv_pci_ioda_dma_dev_setup,

	.dma_bus_setup		= pnv_pci_ioda_dma_bus_setup,

	.iommu_bypass_supported	= pnv_pci_ioda_iommu_bypass_supported,

	.setup_msi_irqs		= pnv_setup_msi_irqs,

	.teardown_msi_irqs	= pnv_teardown_msi_irqs,

	.enable_device_hook	= pnv_pci_enable_device_hook,

	.release_device		= pnv_pci_release_device,

	.window_alignment	= pnv_pci_window_alignment,

arch/powerpc/platforms/powernv/pci.c

+0 −67
Original line number Diff line number Diff line
@@ -160,73 +160,6 @@ int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg) 
}

EXPORT_SYMBOL_GPL(pnv_pci_set_power_state);



int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)

{

	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);

	struct msi_desc *entry;

	struct msi_msg msg;

	int hwirq;

	unsigned int virq;

	int rc;



	if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)

		return -ENODEV;



	if (pdev->no_64bit_msi && !phb->msi32_support)

		return -ENODEV;



	for_each_pci_msi_entry(entry, pdev) {

		if (!entry->msi_attrib.is_64 && !phb->msi32_support) {

			pr_warn("%s: Supports only 64-bit MSIs\n",

				pci_name(pdev));

			return -ENXIO;

		}

		hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);

		if (hwirq < 0) {

			pr_warn("%s: Failed to find a free MSI\n",

				pci_name(pdev));

			return -ENOSPC;

		}

		virq = irq_create_mapping(NULL, phb->msi_base + hwirq);

		if (!virq) {

			pr_warn("%s: Failed to map MSI to linux irq\n",

				pci_name(pdev));

			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);

			return -ENOMEM;

		}

		rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,

				    virq, entry->msi_attrib.is_64, &msg);

		if (rc) {

			pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));

			irq_dispose_mapping(virq);

			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);

			return rc;

		}

		irq_set_msi_desc(virq, entry);

		pci_write_msi_msg(virq, &msg);

	}

	return 0;

}



void pnv_teardown_msi_irqs(struct pci_dev *pdev)

{

	struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);

	struct msi_desc *entry;

	irq_hw_number_t hwirq;



	if (WARN_ON(!phb))

		return;



	for_each_pci_msi_entry(entry, pdev) {

		if (!entry->irq)

			continue;

		hwirq = virq_to_hw(entry->irq);

		irq_set_msi_desc(entry->irq, NULL);

		irq_dispose_mapping(entry->irq);

		msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1);

	}

}



/* Nicely print the contents of the PE State Tables (PEST). */

static void pnv_pci_dump_pest(__be64 pestA[], __be64 pestB[], int pest_size)

{

arch/powerpc/platforms/powernv/pci.h

+0 −6
Original line number Diff line number Diff line
@@ -123,11 +123,7 @@ struct pnv_phb { 
#endif



	unsigned int		msi_base;

	unsigned int		msi32_support;

	struct msi_bitmap	msi_bmp;

	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,

			 unsigned int hwirq, unsigned int virq,

			 unsigned int is_64, struct msi_msg *msg);

	int (*init_m64)(struct pnv_phb *phb);

	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);

	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
@@ -289,8 +285,6 @@ extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np); 
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);

extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);



extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);

extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);

extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn);

extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);

extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);