Commit 6d4ee83b authored by Dave Gerlach's avatar Dave Gerlach Committed by Viresh Kumar
Browse files

arm64: dts: ti: k3-am625: Introduce operating-points table 



Introduce an operating-points table for the A53 cores, containing only
frequency values as this platform operates on a fixed voltage for the
CPUs. Also provide opp-supported-hw values to ensure appropriate OPPs
are enabled based on which type of silicon is in use.

The latency between pre and post frequency transition was measured in
CPUFreq driver for all combinations of OPP changes. The average value
was selected as overall clock-latency-ns.

Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
Signed-off-by: default avatarVibhore Vardhan <vibhore@ti.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent e66e20d7

arch/arm64/boot/dts/ti/k3-am625.dtsi

+51 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 135 0>;

		};



		cpu1: cpu@1 {
@@ -62,6 +64,8 @@ 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 136 0>;

		};



		cpu2: cpu@2 {
@@ -76,6 +80,8 @@ 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 137 0>;

		};



		cpu3: cpu@3 {
@@ -90,6 +96,51 @@ 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&L2_0>;

			operating-points-v2 = <&a53_opp_table>;

			clocks = <&k3_clks 138 0>;

		};

	};



	a53_opp_table: opp-table {

		compatible = "operating-points-v2-ti-cpu";

		opp-shared;

		syscon = <&wkup_conf>;



		opp-200000000 {

			opp-hz = /bits/ 64 <200000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-supported-hw = <0x01 0x0007>;

			clock-latency-ns = <6000000>;

		};



		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-supported-hw = <0x01 0x0006>;

			clock-latency-ns = <6000000>;

		};



		opp-1250000000 {

			opp-hz = /bits/ 64 <1250000000>;

			opp-supported-hw = <0x01 0x0004>;

			clock-latency-ns = <6000000>;

			opp-suspend;

		};

	};