Commit 6cfa4536 authored by Sasha Neftin's avatar Sasha Neftin Committed by Tony Nguyen
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Revert "e1000e: Fix possible HW unit hang after an s0ix exit"

This reverts commit 1866aa0d.

Commit 1866aa0d ("e1000e: Fix possible HW unit hang after an s0ix
exit") was a workaround for CSME problem to handle messages comes via H2ME
mailbox. This problem has been fixed by patch "e1000e: Enable the GPT
clock before sending message to the CSME".

Fixes: 3e55d231 ("e1000e: Add handshake with the CSME to support S0ix")
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214821


Signed-off-by: default avatarSasha Neftin <sasha.neftin@intel.com>
Tested-by: default avatarNaama Meir <naamax.meir@linux.intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent b49feacb
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+0 −1
Original line number Diff line number Diff line
@@ -630,7 +630,6 @@ struct e1000_phy_info {
	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool reset_disable;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};
+0 −4
Original line number Diff line number Diff line
@@ -2050,10 +2050,6 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
	bool blocked = false;
	int i = 0;

	/* Check the PHY (LCD) reset flag */
	if (hw->phy.reset_disable)
		return true;

	while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
	       (i++ < 30))
		usleep_range(10000, 11000);
+0 −1
Original line number Diff line number Diff line
@@ -271,7 +271,6 @@
#define I217_CGFREG_ENABLE_MTA_RESET	0x0002
#define I217_MEMPWR			PHY_REG(772, 26)
#define I217_MEMPWR_DISABLE_SMB_RELEASE	0x0010
#define I217_MEMPWR_MOEM		0x1000

/* Receive Address Initial CRC Calculation */
#define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
+0 −26
Original line number Diff line number Diff line
@@ -6991,21 +6991,8 @@ static __maybe_unused int e1000e_pm_suspend(struct device *dev)
	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
	struct e1000_adapter *adapter = netdev_priv(netdev);
	struct pci_dev *pdev = to_pci_dev(dev);
	struct e1000_hw *hw = &adapter->hw;
	u16 phy_data;
	int rc;

	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
	    hw->mac.type >= e1000_pch_adp) {
		/* Mask OEM Bits / Gig Disable / Restart AN (772_26[12] = 1) */
		e1e_rphy(hw, I217_MEMPWR, &phy_data);
		phy_data |= I217_MEMPWR_MOEM;
		e1e_wphy(hw, I217_MEMPWR, phy_data);

		/* Disable LCD reset */
		hw->phy.reset_disable = true;
	}

	e1000e_flush_lpic(pdev);

	e1000e_pm_freeze(dev);
@@ -7027,8 +7014,6 @@ static __maybe_unused int e1000e_pm_resume(struct device *dev)
	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
	struct e1000_adapter *adapter = netdev_priv(netdev);
	struct pci_dev *pdev = to_pci_dev(dev);
	struct e1000_hw *hw = &adapter->hw;
	u16 phy_data;
	int rc;

	/* Introduce S0ix implementation */
@@ -7039,17 +7024,6 @@ static __maybe_unused int e1000e_pm_resume(struct device *dev)
	if (rc)
		return rc;

	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
	    hw->mac.type >= e1000_pch_adp) {
		/* Unmask OEM Bits / Gig Disable / Restart AN 772_26[12] = 0 */
		e1e_rphy(hw, I217_MEMPWR, &phy_data);
		phy_data &= ~I217_MEMPWR_MOEM;
		e1e_wphy(hw, I217_MEMPWR, phy_data);

		/* Enable LCD reset */
		hw->phy.reset_disable = false;
	}

	return e1000e_pm_thaw(dev);
}