Commit 6ce2427d authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Update min dcfclk 



[Why]
NV12 has lower min dcfclk

[How]
Add update in update_bounding_box

Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f24b0522

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+8 −4
Original line number Diff line number Diff line
@@ -3084,10 +3084,14 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s 


	if (dc->bb_overrides.min_dcfclk_mhz > 0)

		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;

	else {

		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))

			min_dcfclk = 310;

		else

			// Accounting for SOC/DCF relationship, we can go as high as

		// 506Mhz in Vmin.  We need to code 507 since SMU will round down to 506.

		min_dcfclk = 507;

			// 506Mhz in Vmin.

			min_dcfclk = 506;

	}



	for (i = 0; i < num_states; i++) {

		int min_fclk_required_by_uclk;