Commit 6cdbb101 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/uncore: Associate shadow table with uncore 



Store a reference to a platform's shadow table inside the uncore, the
same as we do with the forcewake table.  This will allow us to use a
single set of functions that operate on the shadow table reference
rather than generating lots of nearly-identical functions via macros
that differ only in terms of the table that they reference.

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210910201030.3436066-3-matthew.d.roper@intel.com
parent 1ab2b4cd

drivers/gpu/drm/i915/intel_uncore.c

+26 −14
Original line number Diff line number Diff line
@@ -1026,17 +1026,16 @@ static int mmio_range_cmp(u32 key, const struct i915_range *range) 
		return 0;

}



#define __is_X_shadowed(x) \

static bool is_##x##_shadowed(u32 offset) \

{ \

	const struct i915_range *regs = x##_shadowed_regs; \

	return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \

		       mmio_range_cmp); \

}

static bool is_shadowed(struct intel_uncore *uncore, u32 offset)

{

	if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table))

		return false;



__is_X_shadowed(gen8)

__is_X_shadowed(gen11)

__is_X_shadowed(gen12)

	return BSEARCH(offset,

		       uncore->shadowed_reg_table,

		       uncore->shadowed_reg_table_entries,

		       mmio_range_cmp);

}



static enum forcewake_domains

gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1047,7 +1046,7 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 
#define __gen8_reg_write_fw_domains(uncore, offset) \

({ \

	enum forcewake_domains __fwd; \

	if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \

	if (NEEDS_FORCE_WAKE(offset) && !is_shadowed(uncore, offset)) \

		__fwd = FORCEWAKE_RENDER; \

	else \

		__fwd = 0; \
@@ -1081,7 +1080,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { 
#define __fwtable_reg_write_fw_domains(uncore, offset) \

({ \

	enum forcewake_domains __fwd = 0; \

	if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \

	if (NEEDS_FORCE_WAKE((offset)) && !is_shadowed(uncore, offset)) \

		__fwd = find_fw_domain(uncore, offset); \

	__fwd; \

})
@@ -1090,7 +1089,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { 
({ \

	enum forcewake_domains __fwd = 0; \

	const u32 __offset = (offset); \

	if (!is_gen11_shadowed(__offset)) \

	if (!is_shadowed(uncore, __offset)) \

		__fwd = find_fw_domain(uncore, __offset); \

	__fwd; \

})
@@ -1099,7 +1098,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = { 
({ \

	enum forcewake_domains __fwd = 0; \

	const u32 __offset = (offset); \

	if (!is_gen12_shadowed(__offset)) \

	if (!is_shadowed(uncore, __offset)) \

		__fwd = find_fw_domain(uncore, __offset); \

	__fwd; \

})
@@ -1969,6 +1968,12 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) 
	(uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \

}



#define ASSIGN_SHADOW_TABLE(uncore, d) \

{ \

	(uncore)->shadowed_reg_table = d; \

	(uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \

}



static int i915_pmic_bus_access_notifier(struct notifier_block *nb,

					 unsigned long action, void *data)

{
@@ -2081,30 +2086,37 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) 


	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);

		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);

	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);

		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);

	} else if (GRAPHICS_VER(i915) >= 12) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);

		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);

	} else if (GRAPHICS_VER(i915) == 11) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);

		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);

	} else if (IS_GRAPHICS_VER(i915, 9, 10)) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);

		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);

	} else if (IS_CHERRYVIEW(i915)) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);

		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);

	} else if (GRAPHICS_VER(i915) == 8) {

		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);

		ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);

		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);

		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);

	} else if (IS_VALLEYVIEW(i915)) {

drivers/gpu/drm/i915/intel_uncore.h

+7 −0
Original line number Diff line number Diff line
@@ -142,6 +142,13 @@ struct intel_uncore { 
	const struct intel_forcewake_range *fw_domains_table;

	unsigned int fw_domains_table_entries;



	/*

	 * Shadowed registers are special cases where we can safely write

	 * to the register *without* grabbing forcewake.

	 */

	const struct i915_range *shadowed_reg_table;

	unsigned int shadowed_reg_table_entries;



	struct notifier_block pmic_bus_access_nb;

	struct intel_uncore_funcs funcs;