Commit 6cd84cfc authored by Vinod Koul's avatar Vinod Koul
Browse files

Merge branch 'fixes' into next

parents bca21e93 38b1927e

drivers/phy/allwinner/phy-sun4i-usb.c

+3 −2
Original line number Diff line number Diff line
@@ -546,13 +546,14 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work) 
	struct sun4i_usb_phy_data *data =

		container_of(work, struct sun4i_usb_phy_data, detect.work);

	struct phy *phy0 = data->phys[0].phy;

	struct sun4i_usb_phy *phy = phy_get_drvdata(phy0);

	struct sun4i_usb_phy *phy;

	bool force_session_end, id_notify = false, vbus_notify = false;

	int id_det, vbus_det;



	if (phy0 == NULL)

	if (!phy0)

		return;



	phy = phy_get_drvdata(phy0);

	id_det = sun4i_usb_phy0_get_id_det(data);

	vbus_det = sun4i_usb_phy0_get_vbus_det(data);

drivers/phy/intel/phy-intel-combo.c

+8 −6
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static inline void combo_phy_w32_off_mask(void __iomem *base, unsigned int reg, 


	reg_val = readl(base + reg);

	reg_val &= ~mask;

	reg_val |= FIELD_PREP(mask, val);

	reg_val |= val;

	writel(reg_val, base + reg);

}
@@ -169,7 +169,7 @@ static int intel_cbphy_pcie_en_pad_refclk(struct intel_cbphy_iphy *iphy) 
		return 0;



	combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,

			       PCIE_PHY_CLK_PAD, 0);

			       PCIE_PHY_CLK_PAD, FIELD_PREP(PCIE_PHY_CLK_PAD, 0));



	/* Delay for stable clock PLL */

	usleep_range(50, 100);
@@ -192,14 +192,14 @@ static int intel_cbphy_pcie_dis_pad_refclk(struct intel_cbphy_iphy *iphy) 
		return 0;



	combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,

			       PCIE_PHY_CLK_PAD, 1);

			       PCIE_PHY_CLK_PAD, FIELD_PREP(PCIE_PHY_CLK_PAD, 1));



	return 0;

}



static int intel_cbphy_set_mode(struct intel_combo_phy *cbphy)

{

	enum intel_combo_mode cb_mode = PHY_PCIE_MODE;

	enum intel_combo_mode cb_mode;

	enum aggregated_mode aggr = cbphy->aggr_mode;

	struct device *dev = cbphy->dev;

	enum intel_phy_mode mode;
@@ -224,6 +224,8 @@ static int intel_cbphy_set_mode(struct intel_combo_phy *cbphy) 


		cb_mode = SATA0_SATA1_MODE;

		break;

	default:

		return -EINVAL;

	}



	ret = regmap_write(cbphy->hsiocfg, REG_COMBO_MODE(cbphy->bid), cb_mode);
@@ -385,7 +387,7 @@ static int intel_cbphy_calibrate(struct phy *phy) 


	/* trigger auto RX adaptation */

	combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),

			       ADAPT_REQ_MSK, 3);

			       ADAPT_REQ_MSK, FIELD_PREP(ADAPT_REQ_MSK, 3));

	/* Wait RX adaptation to finish */

	ret = readl_poll_timeout(cr_base + CR_ADDR(PCS_XF_RX_ADAPT_ACK, id),

				 val, val & RX_ADAPT_ACK_BIT, 10, 5000);
@@ -396,7 +398,7 @@ static int intel_cbphy_calibrate(struct phy *phy) 


	/* Stop RX adaptation */

	combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),

			       ADAPT_REQ_MSK, 0);

			       ADAPT_REQ_MSK, FIELD_PREP(ADAPT_REQ_MSK, 0));



	return ret;

}

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

+2 −2
Original line number Diff line number Diff line
@@ -607,8 +607,8 @@ static int inno_dsidphy_probe(struct platform_device *pdev) 
	platform_set_drvdata(pdev, inno);



	inno->phy_base = devm_platform_ioremap_resource(pdev, 0);

	if (!inno->phy_base)

		return -ENOMEM;

	if (IS_ERR(inno->phy_base))

		return PTR_ERR(inno->phy_base);



	inno->ref_clk = devm_clk_get(dev, "ref");

	if (IS_ERR(inno->ref_clk)) {

drivers/phy/ti/phy-am654-serdes.c

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ struct serdes_am654_clk_mux { 
#define to_serdes_am654_clk_mux(_hw)	\

		container_of(_hw, struct serdes_am654_clk_mux, hw)



static struct regmap_config serdes_am654_regmap_config = {

static const struct regmap_config serdes_am654_regmap_config = {

	.reg_bits = 32,

	.val_bits = 32,

	.reg_stride = 4,

drivers/phy/ti/phy-j721e-wiz.c

+5 −5
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ struct wiz_clk_mux { 
struct wiz_clk_divider {

	struct clk_hw		hw;

	struct regmap_field	*field;

	struct clk_div_table	*table;

	const struct clk_div_table	*table;

	struct clk_init_data	clk_data;

};
@@ -131,7 +131,7 @@ struct wiz_clk_mux_sel { 


struct wiz_clk_div_sel {

	struct regmap_field	*field;

	struct clk_div_table	*table;

	const struct clk_div_table	*table;

	const char		*node_name;

};
@@ -173,7 +173,7 @@ static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 
	},

};



static struct clk_div_table clk_div_table[] = {

static const struct clk_div_table clk_div_table[] = {

	{ .val = 0, .div = 1, },

	{ .val = 1, .div = 2, },

	{ .val = 2, .div = 4, },
@@ -559,7 +559,7 @@ static const struct clk_ops wiz_clk_div_ops = { 


static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,

				struct regmap_field *field,

				struct clk_div_table *table)

				const struct clk_div_table *table)

{

	struct device *dev = wiz->dev;

	struct wiz_clk_divider *div;
@@ -756,7 +756,7 @@ static const struct reset_control_ops wiz_phy_reset_ops = { 
	.deassert = wiz_phy_reset_deassert,

};



static struct regmap_config wiz_regmap_config = {

static const struct regmap_config wiz_regmap_config = {

	.reg_bits = 32,

	.val_bits = 32,

	.reg_stride = 4,